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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-08-05 14:13:41 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-08-05 14:13:41 +1000
commit9287b95ec9ded0a4458094ebd967502263d80112 (patch)
treeb288d670f96376b410fa1980b9413a2360bf4431 /arch/powerpc/kernel/head_64.S
parentea668936b708029a0a11422ff834b651ac434c2d (diff)
parent78eb9094ca08a40b8f9d3e113a2b88e0b7dbad1d (diff)
Merge remote-tracking branch 'scott/next' into next
Scott writes: Highlights include e6500 hardware threading support, an e6500 TLB erratum workaround, corenet error reporting, support for a new board, and some minor fixes.
Diffstat (limited to 'arch/powerpc/kernel/head_64.S')
-rw-r--r--arch/powerpc/kernel/head_64.S22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 41ab76c3a94a..d48125d0c048 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -180,6 +180,28 @@ exception_marker:
#include "exceptions-64s.S"
#endif
+#ifdef CONFIG_PPC_BOOK3E
+_GLOBAL(fsl_secondary_thread_init)
+ /* Enable branch prediction */
+ lis r3,BUCSR_INIT@h
+ ori r3,r3,BUCSR_INIT@l
+ mtspr SPRN_BUCSR,r3
+ isync
+
+ /*
+ * Fix PIR to match the linear numbering in the device tree.
+ *
+ * On e6500, the reset value of PIR uses the low three bits for
+ * the thread within a core, and the upper bits for the core
+ * number. There are two threads per core, so shift everything
+ * but the low bit right by two bits so that the cpu numbering is
+ * continuous.
+ */
+ mfspr r3, SPRN_PIR
+ rlwimi r3, r3, 30, 2, 30
+ mtspr SPRN_PIR, r3
+#endif
+
_GLOBAL(generic_secondary_thread_init)
mr r24,r3