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authorYuanquan Chen <Yuanquan.Chen@freescale.com>2013-05-17 15:35:29 +0800
committerScott Wood <scottwood@freescale.com>2013-08-07 18:38:08 -0500
commit36f684940017b7a5d9039861189203d64d2f8861 (patch)
treefff1dd4c5e9c527bc182223a70fbd1d9ce793046 /arch/powerpc/sysdev
parentc45e91831b80b97116eb2bbab30a95bc88e32f77 (diff)
powerpc/pci: fix PCI-e check link issue
For Freescale powerpc platform, the PCI-e bus number uses the reassign mode by default. It means the second PCI-e controller's hose->first_busno is the first controller's last bus number adding 1. For some hotpluged device(or controlled by FPGA), the device is linked to PCI-e slot at linux runtime. It needs rescan for the system to add it and driver it to work. It successes to rescan the device linked to the first PCI-e controller's slot, but fails to rescan the device linked to the second PCI-e controller's slot. The cause is that the bus->number is reset to 0, which isn't equal to the hose->first_busno for the second controller checking PCI-e link. So it doesn't really check the PCI-e link status, the link status is always no_link. The device won't be really rescaned. Reset the bus->number to hose->first_busno in the function fsl_pcie_check_link(), it will do the real checking PCI-e link status for the second controller, the device will be rescaned. Signed-off-by: Yuanquan Chen <Yuanquan.Chen@freescale.com> Tested-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f32772063d13..ccfb50ddfe38 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -68,7 +68,7 @@ static int fsl_pcie_check_link(struct pci_controller *hose)
if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
if (hose->ops->read == fsl_indirect_read_config) {
struct pci_bus bus;
- bus.number = 0;
+ bus.number = hose->first_busno;
bus.sysdata = hose;
bus.ops = hose->ops;
indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);