diff options
author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2008-08-01 20:42:05 +0200 |
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committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2008-08-01 20:42:05 +0200 |
commit | c6557e7f2b6ae76a44653d38f835174074c42e05 (patch) | |
tree | da619a76b309cb1cd259d082af768a83cfcd6d52 /arch/s390/include/asm/smp.h | |
parent | ab4227cb2d936886069ef1056c02500d05beb15d (diff) |
[S390] move include/asm-s390 to arch/s390/include/asm
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/include/asm/smp.h')
-rw-r--r-- | arch/s390/include/asm/smp.h | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h new file mode 100644 index 000000000000..ae89cf2478fc --- /dev/null +++ b/arch/s390/include/asm/smp.h @@ -0,0 +1,116 @@ +/* + * include/asm-s390/smp.h + * + * S390 version + * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation + * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), + * Martin Schwidefsky (schwidefsky@de.ibm.com) + * Heiko Carstens (heiko.carstens@de.ibm.com) + */ +#ifndef __ASM_SMP_H +#define __ASM_SMP_H + +#include <linux/threads.h> +#include <linux/cpumask.h> +#include <linux/bitops.h> + +#if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__) + +#include <asm/lowcore.h> +#include <asm/sigp.h> +#include <asm/ptrace.h> +#include <asm/system.h> + +/* + s390 specific smp.c headers + */ +typedef struct +{ + int intresting; + sigp_ccode ccode; + __u32 status; + __u16 cpu; +} sigp_info; + +extern void machine_restart_smp(char *); +extern void machine_halt_smp(void); +extern void machine_power_off_smp(void); + +#define NO_PROC_ID 0xFF /* No processor magic marker */ + +/* + * This magic constant controls our willingness to transfer + * a process across CPUs. Such a transfer incurs misses on the L1 + * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My + * gut feeling is this will vary by board in value. For a board + * with separate L2 cache it probably depends also on the RSS, and + * for a board with shared L2 cache it ought to decay fast as other + * processes are run. + */ + +#define PROC_CHANGE_PENALTY 20 /* Schedule penalty */ + +#define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr) + +static inline __u16 hard_smp_processor_id(void) +{ + return stap(); +} + +/* + * returns 1 if cpu is in stopped/check stopped state or not operational + * returns 0 otherwise + */ +static inline int +smp_cpu_not_running(int cpu) +{ + __u32 status; + + switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) { + case sigp_order_code_accepted: + case sigp_status_stored: + /* Check for stopped and check stop state */ + if (status & 0x50) + return 1; + break; + case sigp_not_operational: + return 1; + default: + break; + } + return 0; +} + +#define cpu_logical_map(cpu) (cpu) + +extern int __cpu_disable (void); +extern void __cpu_die (unsigned int cpu); +extern void cpu_die (void) __attribute__ ((noreturn)); +extern int __cpu_up (unsigned int cpu); + +extern struct mutex smp_cpu_state_mutex; +extern int smp_cpu_polarization[]; + +extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *), + void *info, int wait); +#endif + +#ifndef CONFIG_SMP +static inline void smp_send_stop(void) +{ + /* Disable all interrupts/machine checks */ + __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK); +} + +#define hard_smp_processor_id() 0 +#define smp_cpu_not_running(cpu) 1 +#endif + +#ifdef CONFIG_HOTPLUG_CPU +extern int smp_rescan_cpus(void); +#else +static inline int smp_rescan_cpus(void) { return 0; } +#endif + +extern union save_area *zfcpdump_save_areas[NR_CPUS + 1]; +#endif |