diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 16:43:28 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 16:43:28 +0900 |
| commit | 959f85f8a3223c116bbe95dd8a9b207790b5d4d3 (patch) | |
| tree | e7da9ccf292f860bfa0ff9cc8b2682cd1d6bad4d /arch/sh/drivers/pci/fixups-r7780rp.c | |
| parent | e108b2ca2349f510ce7d7f910eda89f71d710d84 (diff) | |
sh: Consolidated SH7751/SH7780 PCI support.
This cleans up quite a lot of the PCI mess that we
currently have, and attempts to consolidate the
duplication in the SH7780 and SH7751 PCI controllers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/fixups-r7780rp.c')
| -rw-r--r-- | arch/sh/drivers/pci/fixups-r7780rp.c | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c index b656b562ec99..3e321df65d22 100644 --- a/arch/sh/drivers/pci/fixups-r7780rp.c +++ b/arch/sh/drivers/pci/fixups-r7780rp.c @@ -4,36 +4,42 @@ * Highlander R7780RP-1 PCI fixups * * Copyright (C) 2003 Lineo uSolutions, Inc. - * Copyright (C) 2004 Paul Mundt + * Copyright (C) 2004 - 2006 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include "pci-sh7780.h" +#include <linux/pci.h> +#include "pci-sh4.h" #include <asm/io.h> int pci_fixup_pcic(void) { - outl(0x000043ff, PCI_REG(SH7780_PCIIMR)); - outl(0x0000380f, PCI_REG(SH7780_PCIAINTM)); + pci_write_reg(0x000043ff, SH4_PCIINTM); + pci_write_reg(0x0000380f, SH4_PCIAINTM); - outl(0xfbb00047, PCI_REG(SH7780_PCICMD)); - outl(0x00000000, PCI_REG(SH7780_PCIIBAR)); + pci_write_reg(0xfbb00047, SH7780_PCICMD); + pci_write_reg(0x00000000, SH7780_PCIIBAR); - outl(0x00011912, PCI_REG(SH7780_PCISVID)); - outl(0x08000000, PCI_REG(SH7780_PCICSCR0)); - outl(0x0000001b, PCI_REG(SH7780_PCICSAR0)); - outl(0xfd000000, PCI_REG(SH7780_PCICSCR1)); - outl(0x0000000f, PCI_REG(SH7780_PCICSAR1)); + pci_write_reg(0x00011912, SH7780_PCISVID); + pci_write_reg(0x08000000, SH7780_PCICSCR0); + pci_write_reg(0x0000001b, SH7780_PCICSAR0); + pci_write_reg(0xfd000000, SH7780_PCICSCR1); + pci_write_reg(0x0000000f, SH7780_PCICSAR1); - outl(0xfd000000, PCI_REG(SH7780_PCIMBR0)); - outl(0x00fc0000, PCI_REG(SH7780_PCIMBMR0)); + pci_write_reg(0xfd000000, SH7780_PCIMBR0); + pci_write_reg(0x00fc0000, SH7780_PCIMBMR0); + +#ifdef CONFIG_32BIT + pci_write_reg(0xc0000000, SH7780_PCIMBR2); + pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); +#endif /* Set IOBR for windows containing area specified in pci.h */ - outl((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1)), PCI_REG(SH7780_PCIIOBR)); - outl(((SH7780_PCI_IO_SIZE-1) & (7<<18)), PCI_REG(SH7780_PCIIOBMR)); + pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), + SH7780_PCIIOBR); + pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); return 0; } - |