Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (38 commits)
  sh: R7785RP board updates.
  sh: Update r7780rp defconfig.
  sh: Add die chain notifiers.
  sh: Fix APM emulation on hp6xx.
  sh: Wire up more IRQs for SH7709.
  sh: Solution Engine 7722 board support.
  sh: Fix r7780rp build.
  sh: kdump support.
  sh: Move clock reporting to its own proc entry.
  sh: Solution Engine SH7705 board and CPU updates.
  serial: sh-sci: Fix module clock refcount for serial console.
  serial: sh-sci: Fix module clock refcounting.
  sh: SH7722 clock framework support.
  sh: hp6xx pata_platform support.
  sh: Obey CONFIG_HZ for HZ definition.
  sh: Fix fstatat64() syscall.
  sh: se7780 PCI support.
  sh: SH7780 Solution Engine board support.
  sh: Add a dummy SH-4 PCIC fixup.
  sh: Tidy up L-BOX area5 addresses.
  ...

16 files changed, 1155 insertions, 54 deletions

diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index abb586b12565..014f318f5a05 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -1,7 +1,7 @@
 /*
  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
  *
- *  Copyright (C) 2005, 2006  Paul Mundt
+ *  Copyright (C) 2005, 2006, 2007  Paul Mundt
  *
  * This clock framework is derived from the OMAP version by:
  *
@@ -23,6 +23,7 @@
 #include <linux/seq_file.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/proc_fs.h>
 #include <asm/clock.h>
 #include <asm/timer.h>
 
@@ -98,15 +99,17 @@ int __clk_enable(struct clk *clk)
 		if (clk->ops && clk->ops->init)
 			clk->ops->init(clk);
 
+	kref_get(&clk->kref);
+
 	if (clk->flags & CLK_ALWAYS_ENABLED)
 		return 0;
 
 	if (likely(clk->ops && clk->ops->enable))
 		clk->ops->enable(clk);
 
-	kref_get(&clk->kref);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(__clk_enable);
 
 int clk_enable(struct clk *clk)
 {
@@ -119,6 +122,7 @@ int clk_enable(struct clk *clk)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(clk_enable);
 
 static void clk_kref_release(struct kref *kref)
 {
@@ -127,11 +131,17 @@ static void clk_kref_release(struct kref *kref)
 
 void __clk_disable(struct clk *clk)
 {
+	int count = kref_put(&clk->kref, clk_kref_release);
+
 	if (clk->flags & CLK_ALWAYS_ENABLED)
 		return;
 
-	kref_put(&clk->kref, clk_kref_release);
+	if (!count) {	/* count reaches zero, disable the clock */
+		if (likely(clk->ops && clk->ops->disable))
+			clk->ops->disable(clk);
+	}
 }
+EXPORT_SYMBOL_GPL(__clk_disable);
 
 void clk_disable(struct clk *clk)
 {
@@ -141,6 +151,7 @@ void clk_disable(struct clk *clk)
 	__clk_disable(clk);
 	spin_unlock_irqrestore(&clock_lock, flags);
 }
+EXPORT_SYMBOL_GPL(clk_disable);
 
 int clk_register(struct clk *clk)
 {
@@ -151,8 +162,18 @@ int clk_register(struct clk *clk)
 
 	mutex_unlock(&clock_list_sem);
 
+	if (clk->flags & CLK_ALWAYS_ENABLED) {
+		pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
+		if (clk->ops && clk->ops->init)
+			clk->ops->init(clk);
+		if (clk->ops && clk->ops->enable)
+			clk->ops->enable(clk);
+		pr_debug( "Enabled.");
+	}
+
 	return 0;
 }
+EXPORT_SYMBOL_GPL(clk_register);
 
 void clk_unregister(struct clk *clk)
 {
@@ -160,21 +181,29 @@ void clk_unregister(struct clk *clk)
 	list_del(&clk->node);
 	mutex_unlock(&clock_list_sem);
 }
+EXPORT_SYMBOL_GPL(clk_unregister);
 
-inline unsigned long clk_get_rate(struct clk *clk)
+unsigned long clk_get_rate(struct clk *clk)
 {
 	return clk->rate;
 }
+EXPORT_SYMBOL_GPL(clk_get_rate);
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
+	return clk_set_rate_ex(clk, rate, 0);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
+{
 	int ret = -EOPNOTSUPP;
 
 	if (likely(clk->ops && clk->ops->set_rate)) {
 		unsigned long flags;
 
 		spin_lock_irqsave(&clock_lock, flags);
-		ret = clk->ops->set_rate(clk, rate);
+		ret = clk->ops->set_rate(clk, rate, algo_id);
 		spin_unlock_irqrestore(&clock_lock, flags);
 	}
 
@@ -183,6 +212,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
 
 void clk_recalc_rate(struct clk *clk)
 {
@@ -197,6 +227,7 @@ void clk_recalc_rate(struct clk *clk)
 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
 		propagate_rate(clk);
 }
+EXPORT_SYMBOL_GPL(clk_recalc_rate);
 
 /*
  * Returns a clock. Note that we first try to use device id on the bus
@@ -233,18 +264,43 @@ found:
 
 	return clk;
 }
+EXPORT_SYMBOL_GPL(clk_get);
 
 void clk_put(struct clk *clk)
 {
 	if (clk && !IS_ERR(clk))
 		module_put(clk->owner);
 }
+EXPORT_SYMBOL_GPL(clk_put);
 
 void __init __attribute__ ((weak))
 arch_init_clk_ops(struct clk_ops **ops, int type)
 {
 }
 
+static int show_clocks(char *buf, char **start, off_t off,
+		       int len, int *eof, void *data)
+{
+	struct clk *clk;
+	char *p = buf;
+
+	list_for_each_entry_reverse(clk, &clock_list, node) {
+		unsigned long rate = clk_get_rate(clk);
+
+		/*
+		 * Don't bother listing dummy clocks with no ancestry
+		 * that only support enable and disable ops.
+		 */
+		if (unlikely(!rate && !clk->parent))
+			continue;
+
+		p += sprintf(p, "%-12s\t: %ld.%02ldMHz\n", clk->name,
+			     rate / 1000000, (rate % 1000000) / 10000);
+	}
+
+	return p - buf;
+}
+
 int __init clk_init(void)
 {
 	int i, ret = 0;
@@ -256,7 +312,6 @@ int __init clk_init(void)
 
 		arch_init_clk_ops(&clk->ops, i);
 		ret |= clk_register(clk);
-		clk_enable(clk);
 	}
 
 	/* Kick the child clocks.. */
@@ -266,35 +321,14 @@ int __init clk_init(void)
 	return ret;
 }
 
-int show_clocks(struct seq_file *m)
+static int __init clk_proc_init(void)
 {
-	struct clk *clk;
-
-	list_for_each_entry_reverse(clk, &clock_list, node) {
-		unsigned long rate = clk_get_rate(clk);
-
-		/*
-		 * Don't bother listing dummy clocks with no ancestry
-		 * that only support enable and disable ops.
-		 */
-		if (unlikely(!rate && !clk->parent))
-			continue;
-
-		seq_printf(m, "%-12s\t: %ld.%02ldMHz\n", clk->name,
-			   rate / 1000000, (rate % 1000000) / 10000);
-	}
+	struct proc_dir_entry *p;
+	p = create_proc_read_entry("clocks", S_IRUSR, NULL,
+				   show_clocks, NULL);
+	if (unlikely(!p))
+		return -EINVAL;
 
 	return 0;
 }
-
-EXPORT_SYMBOL_GPL(clk_register);
-EXPORT_SYMBOL_GPL(clk_unregister);
-EXPORT_SYMBOL_GPL(clk_get);
-EXPORT_SYMBOL_GPL(clk_put);
-EXPORT_SYMBOL_GPL(clk_enable);
-EXPORT_SYMBOL_GPL(clk_disable);
-EXPORT_SYMBOL_GPL(__clk_enable);
-EXPORT_SYMBOL_GPL(__clk_disable);
-EXPORT_SYMBOL_GPL(clk_get_rate);
-EXPORT_SYMBOL_GPL(clk_set_rate);
-EXPORT_SYMBOL_GPL(clk_recalc_rate);
+subsys_initcall(clk_proc_init);
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 726acfcb9b77..6451ad630174 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -41,6 +41,23 @@ __setup("no" __stringify(x), x##_setup);
 onchip_setup(fpu);
 onchip_setup(dsp);
 
+#ifdef CONFIG_SPECULATIVE_EXECUTION
+#define CPUOPM		0xff2f0000
+#define CPUOPM_RABD	(1 << 5)
+
+static void __init speculative_execution_init(void)
+{
+	/* Clear RABD */
+	ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
+
+	/* Flush the update */
+	(void)ctrl_inl(CPUOPM);
+	ctrl_barrier();
+}
+#else
+#define speculative_execution_init()	do { } while (0)
+#endif
+
 /*
  * Generic first-level cache init
  */
@@ -261,4 +278,6 @@ asmlinkage void __init sh_cpu_init(void)
 	 */
 	ubc_wakeup();
 #endif
+
+	speculative_execution_init();
 }
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
index 0049d217561a..1c23308cfc25 100644
--- a/arch/sh/kernel/cpu/irq/Makefile
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -4,6 +4,6 @@
 obj-y	+= imask.o
 
 obj-$(CONFIG_CPU_HAS_IPR_IRQ)		+= ipr.o
-obj-$(CONFIG_CPU_HAS_PINT_IRQ)		+= pint.o
+obj-$(CONFIG_CPU_HAS_PINT_IRQ)		+= pint.o 
 obj-$(CONFIG_CPU_HAS_MASKREG_IRQ)	+= maskreg.o
 obj-$(CONFIG_CPU_HAS_INTC2_IRQ)		+= intc2.o
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index 74defe76a058..d8e22f4ff0f0 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -18,7 +18,8 @@
 #define INTC2_BASE	0xfe080000
 #define INTC2_INTMSK	(INTC2_BASE + 0x40)
 #define INTC2_INTMSKCLR	(INTC2_BASE + 0x60)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define INTC2_BASE	0xffd40000
 #define INTC2_INTMSK	(INTC2_BASE + 0x38)
 #define INTC2_INTMSKCLR	(INTC2_BASE + 0x3c)
diff --git a/arch/sh/kernel/cpu/irq/pint.c b/arch/sh/kernel/cpu/irq/pint.c
index f60007783a21..67602685df1a 100644
--- a/arch/sh/kernel/cpu/irq/pint.c
+++ b/arch/sh/kernel/cpu/irq/pint.c
@@ -18,6 +18,58 @@
 #include <asm/io.h>
 #include <asm/machvec.h>
 
+#if defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define INTC_INTER      0xA4000014UL
+#define INTC_IPRD       0xA4000018UL
+#define INTC_ICR2       0xA4000012UL
+
+/* PFC */
+#define PORT_PACR       0xA4000100UL
+#define PORT_PBCR       0xA4000102UL
+#define PORT_PCCR       0xA4000104UL
+#define PORT_PDCR       0xA4000106UL
+#define PORT_PECR       0xA4000108UL
+#define PORT_PFCR       0xA400010AUL
+#define PORT_PGCR       0xA400010CUL
+#define PORT_PHCR       0xA400010EUL
+#define PORT_PJCR       0xA4000110UL
+#define PORT_PKCR       0xA4000112UL
+#define PORT_PLCR       0xA4000114UL
+#define PORT_PMCR       0xA4000118UL
+#define PORT_PNCR       0xA400011AUL
+#define PORT_PECR2      0xA4050148UL
+#define PORT_PFCR2      0xA405014AUL
+#define PORT_PNCR2      0xA405015AUL
+
+/* I/O port */
+#define PORT_PADR       0xA4000120UL
+#define PORT_PBDR       0xA4000122UL
+#define PORT_PCDR       0xA4000124UL
+#define PORT_PDDR       0xA4000126UL
+#define PORT_PEDR       0xA4000128UL
+#define PORT_PFDR       0xA400012AUL
+#define PORT_PGDR       0xA400012CUL
+#define PORT_PHDR       0xA400012EUL
+#define PORT_PJDR       0xA4000130UL
+#define PORT_PKDR       0xA4000132UL
+#define PORT_PLDR       0xA4000134UL
+#define PORT_PMDR       0xA4000138UL
+#define PORT_PNDR       0xA400013AUL
+
+#define PINT0_IRQ       40
+#define PINT8_IRQ       41
+#define PINT_IRQ_BASE   86
+
+#define PINT0_IPR_ADDR          INTC_IPRD
+#define PINT0_IPR_POS           3
+#define PINT0_PRIORITY      2
+
+#define PINT8_IPR_ADDR          INTC_IPRD
+#define PINT8_IPR_POS           2
+#define PINT8_PRIORITY      2
+
+#endif /* CONFIG_CPU_SUBTYPE_SH7705 */
+
 static unsigned char pint_map[256];
 static unsigned long portcr_mask;
 
@@ -126,7 +178,7 @@ int ipr_irq_demux(int irq)
 	unsigned long creg, dreg, d, sav;
 
 	if (irq == PINT0_IRQ) {
-#if defined(CONFIG_CPU_SUBTYPE_SH7707)
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
 		creg = PORT_PACR;
 		dreg = PORT_PADR;
 #else
@@ -144,7 +196,7 @@ int ipr_irq_demux(int irq)
 
 		return PINT_IRQ_BASE + pint_map[d];
 	} else if (irq == PINT8_IRQ) {
-#if defined(CONFIG_CPU_SUBTYPE_SH7707)
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7707)
 		creg = PORT_PBCR;
 		dreg = PORT_PBDR;
 #else
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 83905e4e4387..09faa056cd43 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708)	+= setup-sh7708.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7709)	+= setup-sh7709.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7300)	+= setup-sh7300.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7710)	+= setup-sh7710.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7712)	+= setup-sh7710.o
 
 # Primary on-chip clocks (common)
 clock-$(CONFIG_CPU_SH3)			:= clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 821b0ab7b528..647623b22edc 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -78,6 +78,9 @@ int __init detect_cpu_and_cache_system(void)
 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
 		current_cpu_data.type = CPU_SH7710;
 #endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7712)
+		current_cpu_data.type = CPU_SH7712;
+#endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
 		current_cpu_data.type = CPU_SH7705;
 
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index a8e41c5241fa..1983fb7ad6ea 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -2,6 +2,7 @@
  * SH7705 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -14,15 +15,15 @@
 
 static struct plat_sci_port sci_platform_data[] = {
 	{
-		.mapbase	= 0xa4400000,
+		.mapbase	= 0xa4410000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.type		= PORT_SCIF,
-		.irqs		= { 52, 53, 55, 54 },
+		.irqs		= { 56, 57, 59 },
 	}, {
-		.mapbase	= 0xa4410000,
+		.mapbase	= 0xa4400000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.type		= PORT_SCIF,
-		.irqs		= { 56, 57, 59, 58 },
+		.irqs		= { 52, 53, 55 },
 	}, {
 		.flags = 0,
 	}
@@ -46,3 +47,48 @@ static int __init sh7705_devices_setup(void)
 				    ARRAY_SIZE(sh7705_devices));
 }
 __initcall(sh7705_devices_setup);
+
+static struct ipr_data sh7705_ipr_map[] = {
+	/* IRQ, IPR-idx, shift, priority */
+	{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
+	{ 17, 0,  8, 2 }, /* TMU1 TUNI */
+	{ 18, 0,  4, 2 }, /* TMU2 TUNI */
+	{ 27, 1, 12, 2 }, /* WDT ITI */
+	{ 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+	{ 21, 0,  0, 2 }, /* RTC PRI (period) */
+	{ 22, 0,  0, 2 }, /* RTC CUI (carry) */
+	{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
+	{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
+	{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
+	{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
+	{ 52, 4,  8, 3 }, /* SCIF0 ERI */
+	{ 53, 4,  8, 3 }, /* SCIF0 RXI */
+	{ 55, 4,  8, 3 }, /* SCIF0 TXI */
+	{ 56, 4,  4, 3 }, /* SCIF1 ERI */
+	{ 57, 4,  4, 3 }, /* SCIF1 RXI */
+	{ 59, 4,  4, 3 }, /* SCIF1 TXI */
+};
+
+static unsigned long ipr_offsets[] = {
+	0xFFFFFEE2	/* 0: IPRA */
+,	0xFFFFFEE4	/* 1: IPRB */
+,	0xA4000016	/* 2: IPRC */
+,	0xA4000018	/* 3: IPRD */
+,	0xA400001A	/* 4: IPRE */
+,	0xA4080000	/* 5: IPRF */
+,	0xA4080002	/* 6: IPRG */
+,	0xA4080004	/* 7: IPRH */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+	if (idx >= ARRAY_SIZE(ipr_offsets))
+		return 0;
+	return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+	make_ipr_irq(sh7705_ipr_map, ARRAY_SIZE(sh7705_ipr_map));
+}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
index dc9b211cf87f..c7d7c35fc834 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
@@ -48,24 +48,33 @@ static struct platform_device *sh7709_devices[] __initdata = {
 static int __init sh7709_devices_setup(void)
 {
 	return platform_add_devices(sh7709_devices,
-				    ARRAY_SIZE(sh7709_devices));
+		ARRAY_SIZE(sh7709_devices));
 }
 __initcall(sh7709_devices_setup);
 
-#define IPRx(A,N) .addr=A, .shift=0*N*-1
+#define IPRx(A,N)	.addr=A, .shift=N
 #define IPRA(N)	IPRx(0xfffffee2UL,N)
 #define IPRB(N)	IPRx(0xfffffee4UL,N)
+#define IPRC(N)	IPRx(0xa4000016UL,N)
+#define IPRD(N)	IPRx(0xa4000018UL,N)
 #define IPRE(N)	IPRx(0xa400001aUL,N)
 
 static struct ipr_data sh7709_ipr_map[] = {
-	[16]		= { IPRA(15-12), 2 }, /* TMU TUNI0 */
-	[17]		= { IPRA(11-8),  4 }, /* TMU TUNI1 */
-	[22]		= { IPRA(3-0),   2 }, /* RTC CUI */
-	[23 ... 26]	= { IPRB(7-4),   3 }, /* SCI */
-	[27]		= { IPRB(15-12), 2 }, /* WDT ITI */
-	[48 ... 51]	= { IPRE(15-12), 7 }, /* DMA */
-	[52 ... 55]	= { IPRE(11-8),  3 }, /* IRDA */
-	[56 ... 59]	= { IPRE(7-4),   3 }, /* SCIF */
+	[16]		= { IPRA(12), 2 }, /* TMU TUNI0 */
+	[17]		= { IPRA(8),  4 }, /* TMU TUNI1 */
+	[18 ... 19]	= { IPRA(4),  1 }, /* TMU TUNI1 */
+	[20 ... 22]	= { IPRA(0),  2 }, /* RTC CUI */
+	[23 ... 26]	= { IPRB(4),  3 }, /* SCI */
+	[27]		= { IPRB(12), 2 }, /* WDT ITI */
+	[32]		= { IPRC(0),  1 }, /* IRQ 0 */
+	[33]		= { IPRC(4),  1 }, /* IRQ 1 */
+	[34]		= { IPRC(8),  1 }, /* IRQ 2 APM */
+	[35]		= { IPRC(12), 1 }, /* IRQ 3 TOUCHSCREEN */
+	[36]		= { IPRD(0),  1 }, /* IRQ 4 */
+	[37]		= { IPRD(4),  1 }, /* IRQ 5 */
+	[48 ... 51]	= { IPRE(12), 7 }, /* DMA */
+	[52 ... 55]	= { IPRE(8),  3 }, /* IRDA */
+	[56 ... 59]	= { IPRE(4),  3 }, /* SCIF */
 };
 
 void __init init_IRQ_ipr()
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 895f99ee6a95..51760a7e7f1c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -2,6 +2,7 @@
  * SH7710 Setup
  *
  *  Copyright (C) 2006  Paul Mundt
+ *  Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -19,6 +20,12 @@ static struct plat_sci_port sci_platform_data[] = {
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {
+		.mapbase	= 0xa4420000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs           = { 56, 57, 59, 58 },
+	}, {
+
 		.flags = 0,
 	}
 };
@@ -41,3 +48,56 @@ static int __init sh7710_devices_setup(void)
 				    ARRAY_SIZE(sh7710_devices));
 }
 __initcall(sh7710_devices_setup);
+
+static struct ipr_data sh7710_ipr_map[] = {
+	/* IRQ, IPR-idx, shift, priority */
+	{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
+	{ 17, 0,  8, 2 }, /* TMU1 TUNI */
+	{ 18, 0,  4, 2 }, /* TMU2 TUNI */
+	{ 27, 1, 12, 2 }, /* WDT ITI */
+	{ 20, 0,  0, 2 }, /* RTC ATI (alarm) */
+	{ 21, 0,  0, 2 }, /* RTC PRI (period) */
+	{ 22, 0,  0, 2 }, /* RTC CUI (carry) */
+	{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
+	{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
+	{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
+	{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
+	{ 52, 4,  8, 3 }, /* SCIF0 ERI */
+	{ 53, 4,  8, 3 }, /* SCIF0 RXI */
+	{ 54, 4,  8, 3 }, /* SCIF0 BRI */
+	{ 55, 4,  8, 3 }, /* SCIF0 TXI */
+	{ 56, 4,  4, 3 }, /* SCIF1 ERI */
+	{ 57, 4,  4, 3 }, /* SCIF1 RXI */
+	{ 58, 4,  4, 3 }, /* SCIF1 BRI */
+	{ 59, 4,  4, 3 }, /* SCIF1 TXI */
+	{ 76, 5,  8, 7 }, /* DMAC DMTE4 */
+	{ 77, 5,  8, 7 }, /* DMAC DMTE5 */
+	{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
+	{ 81, 6,  8, 5 }, /* EDMAC EINT1 */
+	{ 82, 6,  4, 5 }, /* EDMAC EINT2 */
+};
+
+static unsigned long ipr_offsets[] = {
+	0xA414FEE2	/* 0: IPRA */
+,	0xA414FEE4	/* 1: IPRB */
+,	0xA4140016	/* 2: IPRC */
+,	0xA4140018	/* 3: IPRD */
+,	0xA414001A	/* 4: IPRE */
+,	0xA4080000	/* 5: IPRF */
+,	0xA4080002	/* 6: IPRG */
+,	0xA4080004	/* 7: IPRH */
+,	0xA4080006	/* 8: IPRI */
+};
+
+/* given the IPR index return the address of the IPR register */
+unsigned int map_ipridx_to_addr(int idx)
+{
+	if (idx >= ARRAY_SIZE(ipr_offsets))
+		return 0;
+	return ipr_offsets[idx];
+}
+
+void __init init_IRQ_ipr()
+{
+	make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
+}
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index fa2019aabd74..fcb2c41bc34e 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -82,7 +82,8 @@ static void shoc_clk_init(struct clk *clk)
 	for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
 		int divisor = frqcr3_divisors[i];
 
-		if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
+		if (clk->ops->set_rate(clk, clk->parent->rate /
+						divisor, 0) == 0)
 			break;
 	}
 
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 58950de2696d..8cd04904c77a 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -124,6 +124,14 @@ int __init detect_cpu_and_cache_system(void)
 		current_cpu_data.dcache.ways = 4;
 		current_cpu_data.flags |= CPU_HAS_LLSC;
 		break;
+	case 0x3004:
+	case 0x3007:
+		current_cpu_data.type = CPU_SH7785;
+		current_cpu_data.icache.ways = 4;
+		current_cpu_data.dcache.ways = 4;
+		current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+					  CPU_HAS_LLSC;
+		break;
 	case 0x3008:
 		if (prr == 0xa0) {
 			current_cpu_data.type = CPU_SH7722;
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index a8f493f2f21f..ab7422f8f820 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -5,6 +5,7 @@
 # CPU subtype setup
 obj-$(CONFIG_CPU_SUBTYPE_SH7770)	+= setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)	+= setup-sh7780.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7785)	+= setup-sh7785.o
 obj-$(CONFIG_CPU_SUBTYPE_SH73180)	+= setup-sh73180.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)	+= setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)	+= setup-sh7722.o
@@ -13,7 +14,8 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7722)	+= setup-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH73180)	:= clock-sh73180.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7770)	:= clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)	:= clock-sh7780.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7785)	:= clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)	:= clock-sh7343.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7722)	:= clock-sh7343.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7722)	:= clock-sh7722.o
 
 obj-y	+= $(clock-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
new file mode 100644
index 000000000000..29090035bc5b
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -0,0 +1,600 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+ *
+ * SH7722 support for the clock framework
+ *
+ * Copyright (c) 2006-2007 Nomad Global Solutions Inc
+ * Based on code for sh7343 by Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+
+#define SH7722_PLL_FREQ (32000000/8)
+#define N  (-1)
+#define NM (-2)
+#define ROUND_NEAREST 0
+#define ROUND_DOWN -1
+#define ROUND_UP   +1
+
+static int adjust_algos[][3] = {
+	{},	/* NO_CHANGE */
+	{ NM, N, 1 },   /* N:1, N:1 */
+	{ 3, 2, 2 },	/* 3:2:2 */
+	{ 5, 2, 2 },    /* 5:2:2 */
+	{ N, 1, 1 },	/* N:1:1 */
+
+	{ N, 1 },	/* N:1 */
+
+	{ N, 1 },	/* N:1 */
+	{ 3, 2 },
+	{ 4, 3 },
+	{ 5, 4 },
+
+	{ N, 1 }
+};
+
+static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
+			int m1, int m2, int round_flag)
+{
+	unsigned long rem, div;
+	int the_one = 0;
+
+	pr_debug( "Actual values: r1 = %ld\n", r1);
+	pr_debug( "...............r2 = %ld\n", r2);
+
+	if (m1 == m2) {
+		r2 = r1;
+		pr_debug( "setting equal rates: r2 now %ld\n", r2);
+	} else if ((m2 == N  && m1 == 1) ||
+		   (m2 == NM && m1 == N)) { /* N:1 or NM:N */
+		pr_debug( "Setting rates as 1:N (N:N*M)\n");
+		rem = r2 % r1;
+		pr_debug( "...remainder = %ld\n", rem);
+		if (rem) {
+			div = r2 / r1;
+			pr_debug( "...div = %ld\n", div);
+			switch (round_flag) {
+			case ROUND_NEAREST:
+				the_one = rem >= r1/2 ? 1 : 0; break;
+			case ROUND_UP:
+				the_one = 1; break;
+			case ROUND_DOWN:
+				the_one = 0; break;
+			}
+
+			r2 = r1 * (div + the_one);
+			pr_debug( "...setting r2 to %ld\n", r2);
+		}
+	} else if ((m2 == 1  && m1 == N) ||
+		   (m2 == N && m1 == NM)) { /* 1:N or N:NM */
+		pr_debug( "Setting rates as N:1 (N*M:N)\n");
+		rem = r1 % r2;
+		pr_debug( "...remainder = %ld\n", rem);
+		if (rem) {
+			div = r1 / r2;
+			pr_debug( "...div = %ld\n", div);
+			switch (round_flag) {
+			case ROUND_NEAREST:
+				the_one = rem > r2/2 ? 1 : 0; break;
+			case ROUND_UP:
+				the_one = 0; break;
+			case ROUND_DOWN:
+				the_one = 1; break;
+			}
+
+			r2 = r1 / (div + the_one);
+			pr_debug( "...setting r2 to %ld\n", r2);
+		}
+	} else { /* value:value */
+		pr_debug( "Setting rates as %d:%d\n", m1, m2);
+		div = r1 / m1;
+		r2 = div * m2;
+		pr_debug( "...div = %ld\n", div);
+		pr_debug( "...setting r2 to %ld\n", r2);
+	}
+
+	return r2;
+}
+
+static void adjust_clocks(int originate, int *l, unsigned long v[],
+			  int n_in_line)
+{
+	int x;
+
+	pr_debug( "Go down from %d...\n", originate);
+	/* go up recalculation clocks */
+	for (x = originate; x>0; x -- )
+		v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
+					l[x], l[x-1],
+					ROUND_UP);
+
+	pr_debug( "Go up from %d...\n", originate);
+	/* go down recalculation clocks */
+	for (x = originate; x<n_in_line - 1; x ++ )
+		v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
+					l[x], l[x+1],
+					ROUND_UP);
+}
+
+
+/*
+ * SH7722 uses a common set of multipliers and divisors, so this
+ * is quite simple..
+ */
+
+/*
+ * Instead of having two separate multipliers/divisors set, like this:
+ *
+ * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
+ * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
+ *
+ * I created the divisors2 array, which is used to calculate rate like
+ *   rate = parent * 2 / divisors2[ divisor ];
+*/
+static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
+
+static void master_clk_init(struct clk *clk)
+{
+	clk_set_rate(clk, clk_get_rate(clk));
+}
+
+static void master_clk_recalc(struct clk *clk)
+{
+	unsigned long frqcr = ctrl_inl(FRQCR);
+
+	clk->rate = CONFIG_SH_PCLK_FREQ * (1 + (frqcr >> 24 & 0xF));
+}
+
+static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
+{
+	int div = rate / SH7722_PLL_FREQ;
+	int master_divs[] = { 2, 3, 4, 6, 8, 16 };
+	int index;
+	unsigned long frqcr;
+
+	if (rate < SH7722_PLL_FREQ * 2)
+		return -EINVAL;
+
+	for (index = 1; index < ARRAY_SIZE(master_divs); index++)
+		if (div >= master_divs[index - 1] && div < master_divs[index])
+			break;
+
+	if (index >= ARRAY_SIZE(master_divs))
+		index = ARRAY_SIZE(master_divs);
+	div = master_divs[index - 1];
+
+	frqcr = ctrl_inl(FRQCR);
+	frqcr &= ~(0xF << 24);
+	frqcr |= ( (div-1) << 24);
+	ctrl_outl(frqcr, FRQCR);
+
+	return 0;
+}
+
+static struct clk_ops sh7722_master_clk_ops = {
+	.init = master_clk_init,
+	.recalc = master_clk_recalc,
+	.set_rate = master_clk_setrate,
+};
+
+struct frqcr_context {
+	unsigned mask;
+	unsigned shift;
+};
+
+struct frqcr_context sh7722_get_clk_context(const char *name)
+{
+	struct frqcr_context ctx = { 0, };
+
+	if (!strcmp(name, "peripheral_clk")) {
+		ctx.shift = 0;
+		ctx.mask = 0xF;
+	} else if (!strcmp(name, "sdram_clk")) {
+		ctx.shift = 4;
+		ctx.mask = 0xF;
+	} else if (!strcmp(name, "bus_clk")) {
+		ctx.shift = 8;
+		ctx.mask = 0xF;
+	} else if (!strcmp(name, "sh_clk")) {
+		ctx.shift = 12;
+		ctx.mask = 0xF;
+	} else if (!strcmp(name, "umem_clk")) {
+		ctx.shift = 16;
+		ctx.mask = 0xF;
+	} else if (!strcmp(name, "cpu_clk")) {
+		ctx.shift = 20;
+		ctx.mask = 7;
+	}
+	return ctx;
+}
+
+/**
+ * sh7722_find_divisors - find divisor for setting rate
+ *
+ * All sh7722 clocks use the same set of multipliers/divisors. This function
+ * chooses correct divisor to set the rate of clock with parent clock that
+ * generates frequency of 'parent_rate'
+ *
+ * @parent_rate: rate of parent clock
+ * @rate: requested rate to be set
+ */
+static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
+{
+	unsigned div2 = parent_rate * 2 / rate;
+	int index;
+
+	if (rate > parent_rate)
+		return -EINVAL;
+
+	for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
+		if (div2 > divisors2[index] && div2 <= divisors2[index])
+			break;
+	}
+	if (index >= ARRAY_SIZE(divisors2))
+		index = ARRAY_SIZE(divisors2) - 1;
+	return divisors2[index];
+}
+
+static void sh7722_frqcr_recalc(struct clk *clk)
+{
+	struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
+	unsigned long frqcr = ctrl_inl(FRQCR);
+	int index;
+
+	index = (frqcr >> ctx.shift) & ctx.mask;
+	clk->rate = clk->parent->rate * 2 / divisors2[index];
+}
+
+static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
+				 int algo_id)
+{
+	struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
+	unsigned long parent_rate = clk->parent->rate;
+	int div;
+	unsigned long frqcr;
+	int err = 0;
+
+	/* pretty invalid */
+	if (parent_rate < rate)
+		return -EINVAL;
+
+	/* look for multiplier/divisor pair */
+	div = sh7722_find_divisors(parent_rate, rate);
+	if (div<0)
+		return div;
+
+	/* calculate new value of clock rate */
+	clk->rate = parent_rate * 2 / div;
+	frqcr = ctrl_inl(FRQCR);
+
+	/* FIXME: adjust as algo_id specifies */
+	if (algo_id != NO_CHANGE) {
+		int originator;
+		char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
+		char *algo_group_2[] = { "sh_clk", "bus_clk" };
+		char *algo_group_3[] = { "sh_clk", "sdram_clk" };
+		char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
+		char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
+		char **algo_current = NULL;
+		/* 3 is the maximum number of clocks in relation */
+		struct clk *ck[3];
+		unsigned long values[3]; /* the same comment as above */
+		int part_length = -1;
+		int i;
+
+		/*
+		 * all the steps below only required if adjustion was
+		 * requested
+		 */
+		if (algo_id == IUS_N1_N1 ||
+		    algo_id == IUS_322 ||
+		    algo_id == IUS_522 ||
+		    algo_id == IUS_N11) {
+			algo_current = algo_group_1;
+			part_length = 3;
+		}
+		if (algo_id == SB_N1) {
+			algo_current = algo_group_2;
+			part_length = 2;
+		}
+		if (algo_id == SB3_N1 ||
+		    algo_id == SB3_32 ||
+		    algo_id == SB3_43 ||
+		    algo_id == SB3_54) {
+			algo_current = algo_group_3;
+			part_length = 2;
+		}
+		if (algo_id == BP_N1) {
+			algo_current = algo_group_4;
+			part_length = 2;
+		}
+		if (algo_id == IP_N1) {
+			algo_current = algo_group_5;
+			part_length = 2;
+		}
+		if (!algo_current)
+			goto incorrect_algo_id;
+
+		originator = -1;
+		for (i = 0; i < part_length; i ++ ) {
+			if (originator >= 0 && !strcmp(clk->name,
+						       algo_current[i]))
+				originator = i;
+			ck[i] = clk_get(NULL, algo_current[i]);
+			values[i] = clk_get_rate(ck[i]);
+		}
+
+		if (originator >= 0)
+			adjust_clocks(originator, adjust_algos[algo_id],
+				      values, part_length);
+
+		for (i = 0; i < part_length; i ++ ) {
+			struct frqcr_context part_ctx;
+			int part_div;
+
+			if (likely(!err)) {
+				part_div = sh7722_find_divisors(parent_rate,
+								rate);
+				if (part_div > 0) {
+					part_ctx = sh7722_get_clk_context(
+								ck[i]->name);
+					frqcr &= ~(part_ctx.mask <<
+						   part_ctx.shift);
+					frqcr |= part_div << part_ctx.shift;
+				} else
+					err = part_div;
+			}
+
+			ck[i]->ops->recalc(ck[i]);
+			clk_put(ck[i]);
+		}
+	}
+
+	/* was there any error during recalculation ? If so, bail out.. */
+	if (unlikely(err!=0))
+		goto out_err;
+
+	/* clear FRQCR bits */
+	frqcr &= ~(ctx.mask << ctx.shift);
+	frqcr |= div << ctx.shift;
+
+	/* ...and perform actual change */
+	ctrl_outl(frqcr, FRQCR);
+	return 0;
+
+incorrect_algo_id:
+	return -EINVAL;
+out_err:
+	return err;
+}
+
+static struct clk_ops sh7722_frqcr_clk_ops = {
+	.recalc = sh7722_frqcr_recalc,
+	.set_rate = sh7722_frqcr_set_rate,
+};
+
+/*
+ * clock ops methods for SIU A/B and IrDA clock
+ *
+ */
+static int sh7722_siu_which(struct clk *clk)
+{
+	if (!strcmp(clk->name, "siu_a_clk"))
+		return 0;
+	if (!strcmp(clk->name, "siu_b_clk"))
+		return 1;
+	if (!strcmp(clk->name, "irda_clk"))
+		return 2;
+	return -EINVAL;
+}
+
+static unsigned long sh7722_siu_regs[] = {
+	[0] = SCLKACR,
+	[1] = SCLKBCR,
+	[2] = IrDACLKCR,
+};
+
+static int sh7722_siu_start_stop(struct clk *clk, int enable)
+{
+	int siu = sh7722_siu_which(clk);
+	unsigned long r;
+
+	if (siu < 0)
+		return siu;
+	BUG_ON(siu > 2);
+	r = ctrl_inl(sh7722_siu_regs[siu]);
+	if (enable)
+		ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]);
+	else
+		ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]);
+	return 0;
+}
+
+static void sh7722_siu_enable(struct clk *clk)
+{
+	sh7722_siu_start_stop(clk, 1);
+}
+
+static void sh7722_siu_disable(struct clk *clk)
+{
+	sh7722_siu_start_stop(clk, 0);
+}
+
+static void sh7722_video_enable(struct clk *clk)
+{
+	unsigned long r;
+
+	r = ctrl_inl(VCLKCR);
+	ctrl_outl( r & ~(1<<8), VCLKCR);
+}
+
+static void sh7722_video_disable(struct clk *clk)
+{
+	unsigned long r;
+
+	r = ctrl_inl(VCLKCR);
+	ctrl_outl( r | (1<<8), VCLKCR);
+}
+
+static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
+				 int algo_id)
+{
+	unsigned long r;
+
+	r = ctrl_inl(VCLKCR);
+	r &= ~0x3F;
+	r |= ((clk->parent->rate / rate - 1) & 0x3F);
+	ctrl_outl(r, VCLKCR);
+	return 0;
+}
+
+static void sh7722_video_recalc(struct clk *clk)
+{
+	unsigned long r;
+
+	r = ctrl_inl(VCLKCR);
+	clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
+}
+
+static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
+{
+	int siu = sh7722_siu_which(clk);
+	unsigned long r;
+	int div;
+
+	if (siu < 0)
+		return siu;
+	BUG_ON(siu > 2);
+	r = ctrl_inl(sh7722_siu_regs[siu]);
+	div = sh7722_find_divisors(clk->parent->rate, rate);
+	if (div < 0)
+		return div;
+	r = (r & ~0xF) | div;
+	ctrl_outl(r, sh7722_siu_regs[siu]);
+	return 0;
+}
+
+static void sh7722_siu_recalc(struct clk *clk)
+{
+	int siu = sh7722_siu_which(clk);
+	unsigned long r;
+
+	if (siu < 0)
+		return /* siu */ ;
+	BUG_ON(siu > 1);
+	r = ctrl_inl(sh7722_siu_regs[siu]);
+	clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
+}
+
+static struct clk_ops sh7722_siu_clk_ops = {
+	.recalc = sh7722_siu_recalc,
+	.set_rate = sh7722_siu_set_rate,
+	.enable = sh7722_siu_enable,
+	.disable = sh7722_siu_disable,
+};
+
+static struct clk_ops sh7722_video_clk_ops = {
+	.recalc = sh7722_video_recalc,
+	.set_rate = sh7722_video_set_rate,
+	.enable = sh7722_video_enable,
+	.disable = sh7722_video_disable,
+};
+/*
+ * and at last, clock definitions themselves
+ */
+static struct clk sh7722_umem_clock = {
+	.name = "umem_clk",
+	.ops = &sh7722_frqcr_clk_ops,
+};
+
+static struct clk sh7722_sh_clock = {
+	.name = "sh_clk",
+	.ops = &sh7722_frqcr_clk_ops,
+};
+
+static struct clk sh7722_peripheral_clock = {
+	.name = "peripheral_clk",
+	.ops = &sh7722_frqcr_clk_ops,
+};
+
+static struct clk sh7722_sdram_clock = {
+	.name = "sdram_clk",
+	.ops = &sh7722_frqcr_clk_ops,
+};
+
+/*
+ * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
+ * methods of clk_ops determine which register they should access by
+ * examining clk->name field
+ */
+static struct clk sh7722_siu_a_clock = {
+	.name = "siu_a_clk",
+	.ops = &sh7722_siu_clk_ops,
+};
+
+static struct clk sh7722_siu_b_clock = {
+	.name = "siu_b_clk",
+	.ops = &sh7722_siu_clk_ops,
+};
+
+static struct clk sh7722_irda_clock = {
+	.name = "irda_clk",
+	.ops = &sh7722_siu_clk_ops,
+};
+
+static struct clk sh7722_video_clock = {
+	.name = "video_clk",
+	.ops = &sh7722_video_clk_ops,
+};
+
+static struct clk *sh7722_clocks[] = {
+	&sh7722_umem_clock,
+	&sh7722_sh_clock,
+	&sh7722_peripheral_clock,
+	&sh7722_sdram_clock,
+	&sh7722_siu_a_clock,
+	&sh7722_siu_b_clock,
+	&sh7722_irda_clock,
+	&sh7722_video_clock,
+};
+
+/*
+ * init in order: master, module, bus, cpu
+ */
+struct clk_ops *onchip_ops[] = {
+	&sh7722_master_clk_ops,
+	&sh7722_frqcr_clk_ops,
+	&sh7722_frqcr_clk_ops,
+	&sh7722_frqcr_clk_ops,
+};
+
+void __init
+arch_init_clk_ops(struct clk_ops **ops, int type)
+{
+	BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
+	*ops = onchip_ops[type];
+}
+
+int __init sh7722_clock_init(void)
+{
+	struct clk *master;
+	int i;
+
+	master = clk_get(NULL, "master_clk");
+	for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
+		pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
+		sh7722_clocks[i]->parent = master;
+		clk_register(sh7722_clocks[i]);
+	}
+	clk_put(master);
+	return 0;
+}
+arch_initcall(sh7722_clock_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
new file mode 100644
index 000000000000..805535aa505e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -0,0 +1,162 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+ *
+ * SH7785 support for the clock framework
+ *
+ *  Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+#include <asm/io.h>
+
+static int ifc_divisors[] = { 1, 2, 4, 6 };
+static int ufc_divisors[] = { 1, 1, 4, 6 };
+static int sfc_divisors[] = { 1, 1, 4, 6 };
+static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
+			     24, 32, 36, 48, 1, 1, 1, 1 };
+static int mfc_divisors[] = { 1, 1, 4, 6 };
+static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
+			      24, 32, 36, 48, 1, 1, 1, 1 };
+
+static void master_clk_init(struct clk *clk)
+{
+	clk->rate *= 36;
+}
+
+static struct clk_ops sh7785_master_clk_ops = {
+	.init		= master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+	int idx = (ctrl_inl(FRQMR1) & 0x000f);
+	clk->rate = clk->parent->rate / pfc_divisors[idx];
+}
+
+static struct clk_ops sh7785_module_clk_ops = {
+	.recalc		= module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
+	clk->rate = clk->parent->rate / bfc_divisors[idx];
+}
+
+static struct clk_ops sh7785_bus_clk_ops = {
+	.recalc		= bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
+	clk->rate = clk->parent->rate / ifc_divisors[idx];
+}
+
+static struct clk_ops sh7785_cpu_clk_ops = {
+	.recalc		= cpu_clk_recalc,
+};
+
+static struct clk_ops *sh7785_clk_ops[] = {
+	&sh7785_master_clk_ops,
+	&sh7785_module_clk_ops,
+	&sh7785_bus_clk_ops,
+	&sh7785_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+	if (idx < ARRAY_SIZE(sh7785_clk_ops))
+		*ops = sh7785_clk_ops[idx];
+}
+
+static void shyway_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
+	clk->rate = clk->parent->rate / sfc_divisors[idx];
+}
+
+static struct clk_ops sh7785_shyway_clk_ops = {
+	.recalc		= shyway_clk_recalc,
+};
+
+static struct clk sh7785_shyway_clk = {
+	.name		= "shyway_clk",
+	.flags		= CLK_ALWAYS_ENABLED,
+	.ops		= &sh7785_shyway_clk_ops,
+};
+
+static void ddr_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
+	clk->rate = clk->parent->rate / mfc_divisors[idx];
+}
+
+static struct clk_ops sh7785_ddr_clk_ops = {
+	.recalc		= ddr_clk_recalc,
+};
+
+static struct clk sh7785_ddr_clk = {
+	.name		= "ddr_clk",
+	.flags		= CLK_ALWAYS_ENABLED,
+	.ops		= &sh7785_ddr_clk_ops,
+};
+
+static void ram_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
+	clk->rate = clk->parent->rate / ufc_divisors[idx];
+}
+
+static struct clk_ops sh7785_ram_clk_ops = {
+	.recalc		= ram_clk_recalc,
+};
+
+static struct clk sh7785_ram_clk = {
+	.name		= "ram_clk",
+	.flags		= CLK_ALWAYS_ENABLED,
+	.ops		= &sh7785_ram_clk_ops,
+};
+
+/*
+ * Additional SH7785-specific on-chip clocks that aren't already part of the
+ * clock framework
+ */
+static struct clk *sh7785_onchip_clocks[] = {
+	&sh7785_shyway_clk,
+	&sh7785_ddr_clk,
+	&sh7785_ram_clk,
+};
+
+static int __init sh7785_clk_init(void)
+{
+	struct clk *clk = clk_get(NULL, "master_clk");
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
+		struct clk *clkp = sh7785_onchip_clocks[i];
+
+		clkp->parent = clk;
+		clk_register(clkp);
+		clk_enable(clkp);
+	}
+
+	/*
+	 * Now that we have the rest of the clocks registered, we need to
+	 * force the parent clock to propagate so that these clocks will
+	 * automatically figure out their rate. We cheat by handing the
+	 * parent clock its current rate and forcing child propagation.
+	 */
+	clk_set_rate(clk, clk_get_rate(clk));
+
+	clk_put(clk);
+
+	return 0;
+}
+arch_initcall(sh7785_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
new file mode 100644
index 000000000000..07b0de82cfe6
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -0,0 +1,103 @@
+/*
+ * SH7785 Setup
+ *
+ *  Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <asm/sci.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+	{
+		.mapbase	= 0xffea0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 40, 41, 43, 42 },
+	}, {
+		.mapbase	= 0xffeb0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 44, 45, 47, 46 },
+	},
+
+	/*
+	 * The rest of these all have multiplexed IRQs
+	 */
+	{
+		.mapbase	= 0xffec0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 60, 60, 60, 60 },
+	}, {
+		.mapbase	= 0xffed0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 61, 61, 61, 61 },
+	}, {
+		.mapbase	= 0xffee0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 62, 62, 62, 62 },
+	}, {
+		.mapbase	= 0xffef0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 63, 63, 63, 63 },
+	}, {
+		.flags = 0,
+	}
+};
+
+static struct platform_device sci_device = {
+	.name		= "sh-sci",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= sci_platform_data,
+	},
+};
+
+static struct platform_device *sh7785_devices[] __initdata = {
+	&sci_device,
+};
+
+static int __init sh7785_devices_setup(void)
+{
+	return platform_add_devices(sh7785_devices,
+				    ARRAY_SIZE(sh7785_devices));
+}
+__initcall(sh7785_devices_setup);
+
+static struct intc2_data intc2_irq_table[] = {
+	{ 28, 0, 24, 0, 0, 2 },		/* TMU0 */
+
+	{ 40, 8, 24, 0, 2, 3 },		/* SCIF0 ERI */
+	{ 41, 8, 24, 0, 2, 3 },		/* SCIF0 RXI */
+	{ 42, 8, 24, 0, 2, 3 },		/* SCIF0 BRI */
+	{ 43, 8, 24, 0, 2, 3 },		/* SCIF0 TXI */
+
+	{ 44, 8, 16, 0, 3, 3 },		/* SCIF1 ERI */
+	{ 45, 8, 16, 0, 3, 3 },		/* SCIF1 RXI */
+	{ 46, 8, 16, 0, 3, 3 },		/* SCIF1 BRI */
+	{ 47, 8, 16, 0, 3, 3 },		/* SCIF1 TXI */
+
+	{ 64, 0x14,  8, 0, 14, 2 },	/* PCIC0 */
+	{ 65, 0x14,  0, 0, 15, 2 },	/* PCIC1 */
+	{ 66, 0x18, 24, 0, 16, 2 },	/* PCIC2 */
+	{ 67, 0x18, 16, 0, 17, 2 },	/* PCIC3 */
+	{ 68, 0x18,  8, 0, 18, 2 },	/* PCIC4 */
+
+	{ 60,  8,  8, 0, 4, 3 },	/* SCIF2 ERI, RXI, BRI, TXI */
+	{ 60,  8,  0, 0, 5, 3 },	/* SCIF3 ERI, RXI, BRI, TXI */
+	{ 60, 12, 24, 0, 6, 3 },	/* SCIF4 ERI, RXI, BRI, TXI */
+	{ 60, 12, 16, 0, 7, 3 },	/* SCIF5 ERI, RXI, BRI, TXI */
+};
+
+void __init init_IRQ_intc2(void)
+{
+	make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
+}