diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2007-05-09 02:35:27 -0700 |
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committer | David S. Miller <davem@sunset.davemloft.net> | 2007-05-09 02:35:27 -0700 |
commit | ca3dd88e411648c76e1911a729440e3763ba5049 (patch) | |
tree | e874ed0c1e91269aa514a443358d4f3738bcb244 /arch/sparc64/kernel/pci_fire.c | |
parent | de372ecd80a42c4fb485c7232475301a18d05184 (diff) |
[SPARC64] PCI: Consolidate PCI access code into pci_common.c
All the sun4u controllers do the same thing to compute the physical
I/O address to poke, and we can move the sun4v code into this common
location too.
This one needs a bit of testing, in particular the Sabre code had some
funny stuff that would break up u16 and/or u32 accesses into pieces
and I didn't think that was needed any more. If it is we need to find
out why and add back code to do it again.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_fire.c')
-rw-r--r-- | arch/sparc64/kernel/pci_fire.c | 135 |
1 files changed, 2 insertions, 133 deletions
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c index 2e0eb4ee8f71..9198c1a0f7a5 100644 --- a/arch/sparc64/kernel/pci_fire.c +++ b/arch/sparc64/kernel/pci_fire.c @@ -27,138 +27,6 @@ "i" (ASI_PHYS_BYPASS_EC_E) \ : "memory") -/* Fire config space address format is nearly identical to - * that of SCHIZO and PSYCHO, except that in order to accomodate - * PCI-E extended config space the encoding can handle 12 bits - * of register address: - * - * 32 28 27 20 19 15 14 12 11 2 1 0 - * ------------------------------------------------- - * |0 0 0 0 0| bus | device | function | reg | 0 0 | - * ------------------------------------------------- - */ -#define FIRE_CONFIG_BASE(PBM) ((PBM)->config_space) -#define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ - (((unsigned long)(BUS) << 20) | \ - ((unsigned long)(DEVFN) << 12) | \ - ((unsigned long)(REG))) - -static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm, - unsigned char bus, - unsigned int devfn, - int where) -{ - if (!pbm) - return NULL; - return (void *) - (FIRE_CONFIG_BASE(pbm) | - FIRE_CONFIG_ENCODE(bus, devfn, where)); -} - -/* FIRE PCI configuration space accessors. */ - -static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, - int where, int size, u32 *value) -{ - struct pci_pbm_info *pbm = bus_dev->sysdata; - unsigned char bus = bus_dev->number; - u32 *addr; - u16 tmp16; - u8 tmp8; - - if (bus_dev == pbm->pci_bus && devfn == 0x00) - return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where, - size, value); - switch (size) { - case 1: - *value = 0xff; - break; - case 2: - *value = 0xffff; - break; - case 4: - *value = 0xffffffff; - break; - } - - addr = fire_pci_config_mkaddr(pbm, bus, devfn, where); - if (!addr) - return PCIBIOS_SUCCESSFUL; - - switch (size) { - case 1: - pci_config_read8((u8 *)addr, &tmp8); - *value = tmp8; - break; - - case 2: - if (where & 0x01) { - printk("pci_read_config_word: misaligned reg [%x]\n", - where); - return PCIBIOS_SUCCESSFUL; - } - pci_config_read16((u16 *)addr, &tmp16); - *value = tmp16; - break; - - case 4: - if (where & 0x03) { - printk("pci_read_config_dword: misaligned reg [%x]\n", - where); - return PCIBIOS_SUCCESSFUL; - } - - pci_config_read32(addr, value); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, - int where, int size, u32 value) -{ - struct pci_pbm_info *pbm = bus_dev->sysdata; - unsigned char bus = bus_dev->number; - u32 *addr; - - if (bus_dev == pbm->pci_bus && devfn == 0x00) - return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where, - size, value); - addr = fire_pci_config_mkaddr(pbm, bus, devfn, where); - if (!addr) - return PCIBIOS_SUCCESSFUL; - - switch (size) { - case 1: - pci_config_write8((u8 *)addr, value); - break; - - case 2: - if (where & 0x01) { - printk("pci_write_config_word: misaligned reg [%x]\n", - where); - return PCIBIOS_SUCCESSFUL; - } - pci_config_write16((u16 *)addr, value); - break; - - case 4: - if (where & 0x03) { - printk("pci_write_config_dword: misaligned reg [%x]\n", - where); - return PCIBIOS_SUCCESSFUL; - } - - pci_config_write32(addr, value); - } - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops pci_fire_ops = { - .read = fire_read_pci_cfg, - .write = fire_write_pci_cfg, -}; - static void pci_fire_scan_bus(struct pci_pbm_info *pbm) { pbm->pci_bus = pci_scan_one_pbm(pbm); @@ -314,7 +182,8 @@ static void pci_fire_pbm_init(struct pci_controller_info *p, pci_pbm_root = pbm; pbm->scan_bus = pci_fire_scan_bus; - pbm->pci_ops = &pci_fire_ops; + pbm->pci_ops = &sun4u_pci_ops; + pbm->config_space_reg_bits = 12; pbm->index = pci_num_pbms++; |