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authorChris Metcalf <cmetcalf@tilera.com>2013-08-09 16:09:41 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-08-30 11:56:34 -0400
commitabe3265a6d2e5e805361e0fea3346622f3199d68 (patch)
treeff4c4463c2715fc06a62916a4a9d5fa28c996214 /arch/tile
parent6f0142d501b35468d910b9f36b6853dbd8dc5ad5 (diff)
tile: do less L1 I-cache eviction
We had been doing an automatic full eviction of the L1 I$ everywhere whenever we did a kernel-space TLB flush. It turns out this isn't necessary, since all the callers already handle doing a flush if necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/kernel/tlb.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
index 3fd54d5bbd4c..f23b53515671 100644
--- a/arch/tile/kernel/tlb.c
+++ b/arch/tile/kernel/tlb.c
@@ -91,8 +91,14 @@ void flush_tlb_all(void)
}
}
+/*
+ * Callers need to flush the L1I themselves if necessary, e.g. for
+ * kernel module unload. Otherwise we assume callers are not using
+ * executable pgprot_t's. Using EVICT_L1I means that dataplane cpus
+ * will get an unnecessary interrupt otherwise.
+ */
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
- flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
+ flush_remote(0, 0, NULL,
start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);
}