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| author | Ingo Molnar <mingo@elte.hu> | 2008-11-10 09:10:44 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-11-10 09:10:44 +0100 |
| commit | a5a64498c194c82ecad3a2d67cff6231cda8d3dd (patch) | |
| tree | 723d5d81419f9960b8d30ed9a2ece8a58d6c4328 /arch/um/include/asm/cache.h | |
| parent | bb93d802ae5c1949977cc6da247b218240677f11 (diff) | |
| parent | f7160c7573615ec82c691e294cf80d920b5d588d (diff) | |
Merge commit 'v2.6.28-rc4' into timers/rtc
Conflicts:
drivers/rtc/rtc-cmos.c
Diffstat (limited to 'arch/um/include/asm/cache.h')
| -rw-r--r-- | arch/um/include/asm/cache.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/um/include/asm/cache.h b/arch/um/include/asm/cache.h new file mode 100644 index 000000000000..19e1bdd67416 --- /dev/null +++ b/arch/um/include/asm/cache.h @@ -0,0 +1,17 @@ +#ifndef __UM_CACHE_H +#define __UM_CACHE_H + + +#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) +# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) +#elif defined(CONFIG_UML_X86) /* 64-bit */ +# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ +#else +/* XXX: this was taken from x86, now it's completely random. Luckily only + * affects SMP padding. */ +# define L1_CACHE_SHIFT 5 +#endif + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif |