diff options
| author | Andi Kleen <andi@firstfloor.org> | 2009-02-12 13:49:35 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-02-24 13:41:00 -0800 |
| commit | 03195c6b40f2b4db92545921daa7c3a19b4e4c32 (patch) | |
| tree | 895b6a502a4cfe05e4c667f7eb093b74eecef31c /arch/x86/include/asm/apicdef.h | |
| parent | ee031c31d6381d004bfd386c2e45821211507499 (diff) | |
x86, mce, cmci: define MSR names and fields for new CMCI registers
Impact: New register definitions only
CMCI means support for raising an interrupt on a corrected machine
check event instead of having to poll for it. It's a new feature in
Intel Nehalem CPUs available on some machine check banks.
For details see the IA32 SDM Vol3a 14.5
Define the registers for it as a preparation for further patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/apicdef.h')
| -rw-r--r-- | arch/x86/include/asm/apicdef.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 63134e31e8b9..bc9514fb3b13 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -53,6 +53,7 @@ #define APIC_ESR_SENDILL 0x00020 #define APIC_ESR_RECVILL 0x00040 #define APIC_ESR_ILLREGA 0x00080 +#define APIC_LVTCMCI 0x2f0 #define APIC_ICR 0x300 #define APIC_DEST_SELF 0x40000 #define APIC_DEST_ALLINC 0x80000 |