diff options
author | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
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committer | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
commit | 239060b93bb30a4ad55f1ecaa512464a035cc5ba (patch) | |
tree | 77f79810e57d4fc24356eca0cd6db463e8994128 /arch/x86/include/asm/mrst.h | |
parent | 1408b15b98635a13bad2e2a50b3c2ae2ccdf625b (diff) | |
parent | e9203c988234aa512bd45ca32b52e21c7bbfc414 (diff) |
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
Diffstat (limited to 'arch/x86/include/asm/mrst.h')
-rw-r--r-- | arch/x86/include/asm/mrst.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h index 451d30e7f62d..16350740edf6 100644 --- a/arch/x86/include/asm/mrst.h +++ b/arch/x86/include/asm/mrst.h @@ -13,6 +13,32 @@ extern int pci_mrst_init(void); int __init sfi_parse_mrtc(struct sfi_table_header *table); +/* + * Medfield is the follow-up of Moorestown, it combines two chip solution into + * one. Other than that it also added always-on and constant tsc and lapic + * timers. Medfield is the platform name, and the chip name is called Penwell + * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be + * identified via MSRs. + */ +enum mrst_cpu_type { + MRST_CPU_CHIP_LINCROFT = 1, + MRST_CPU_CHIP_PENWELL, +}; + +extern enum mrst_cpu_type __mrst_cpu_chip; +static enum mrst_cpu_type mrst_identify_cpu(void) +{ + return __mrst_cpu_chip; +} + +enum mrst_timer_options { + MRST_TIMER_DEFAULT, + MRST_TIMER_APBT_ONLY, + MRST_TIMER_LAPIC_APBT, +}; + +extern enum mrst_timer_options mrst_timer_options; + #define SFI_MTMR_MAX_NUM 8 #define SFI_MRTC_MAX 8 |