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authorThomas Gleixner <tglx@linutronix.de>2018-05-29 17:50:22 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-08-15 18:14:45 +0200
commit7b69a96e5a328f17fe33f3826d7e8349ab59015d (patch)
treea8f09be1ff2ed4561a1511e4efa7de3183e26568 /arch/x86/include/asm/vm86.h
parent1ac1dc14671f531134f29755f98386f8e168b810 (diff)
x86/smp: Provide topology_is_primary_thread()
commit 6a4d2657e048f096c7ffcad254010bd94891c8c0 upstream If the CPU is supporting SMT then the primary thread can be found by checking the lower APIC ID bits for zero. smp_num_siblings is used to build the mask for the APIC ID bits which need to be taken into account. This uses the MPTABLE or ACPI/MADT supplied APIC ID, which can be different than the initial APIC ID in CPUID. But according to AMD the lower bits have to be consistent. Intel gave a tentative confirmation as well. Preparatory patch to support disabling SMT at boot/runtime. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Acked-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/x86/include/asm/vm86.h')
0 files changed, 0 insertions, 0 deletions