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authorBenson Leung <bleung@chromium.org>2018-07-09 16:36:00 -0700
committerBenson Leung <bleung@chromium.org>2018-07-09 16:36:00 -0700
commit40291fb75123816b35ba06696e56b9cf2d96bf90 (patch)
treedfff532af8df1c06ca83466c8347873426a81579 /arch/x86/kernel/quirks.c
parentc474e9f2be9992861d926eea3e5d4fb393cd6e2a (diff)
parent413c94469a9db26ac4e1d16bf8de0248de93e2d8 (diff)
Merge tag 'ib-platform-chrome-mfd-move-cros-ec-transport-for-4.19' into working-branch-for-4.19
Immutable branch (mfd, chrome) due for the v4.19 window Immutable Branch which moves the cros_ec_i2c and cros_ec_spi transport drivers from mfd to platform/chrome. Changes in arm are a simple rename in defconfigs. Change in input is a rename in help text.
Diffstat (limited to 'arch/x86/kernel/quirks.c')
-rw-r--r--arch/x86/kernel/quirks.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 697a4ce04308..736348ead421 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -645,12 +645,19 @@ static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev)
/* Skylake */
static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
{
- u32 capid0;
+ u32 capid0, capid5;
pci_read_config_dword(pdev, 0x84, &capid0);
+ pci_read_config_dword(pdev, 0x98, &capid5);
- if ((capid0 & 0xc0) == 0xc0)
+ /*
+ * CAPID0{7:6} indicate whether this is an advanced RAS SKU
+ * CAPID5{8:5} indicate that various NVDIMM usage modes are
+ * enabled, so memory machine check recovery is also enabled.
+ */
+ if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
static_branch_inc(&mcsafe_key);
+
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);