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authorIngo Molnar <mingo@elte.hu>2009-01-28 05:01:41 +0100
committerIngo Molnar <mingo@elte.hu>2009-01-28 23:20:17 +0100
commitf6f52baf2613dd319e9ba3f3319bf1f1c442e4b3 (patch)
tree1eb8f814939501c10f3f18af86f9c5a5d25c7310 /arch/x86/mach-generic/es7000.c
parentfe402e1f2b67a63f1e53ab2a316fc20f7ca4ec91 (diff)
x86: clean up esr_disable() methods
Impact: cleanup Most subarchitectures want to disable the APIC ESR (Error Status Register), because they generally have hardware hacks that wrap standard CPUs into a bigger system and hence the APIC bus is quite non-standard and weirdnesses (lockups) have been seen with ESR reporting. Remove the esr_disable macros and put the desired flag into each subarchitecture's genapic template directly. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/mach-generic/es7000.c')
-rw-r--r--arch/x86/mach-generic/es7000.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c
index e31f0c35470d..e8aa8fd4f49f 100644
--- a/arch/x86/mach-generic/es7000.c
+++ b/arch/x86/mach-generic/es7000.c
@@ -112,7 +112,7 @@ struct genapic apic_es7000 = {
.irq_dest_mode = 0,
.target_cpus = es7000_target_cpus,
- .ESR_DISABLE = esr_disable,
+ .ESR_DISABLE = 1,
.apic_destination_logical = APIC_DEST_LOGICAL,
.check_apicid_used = check_apicid_used,
.check_apicid_present = check_apicid_present,