diff options
| author | Alan Cox <alan@linux.intel.com> | 2012-02-13 12:59:37 +0000 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-02-23 12:33:27 -0800 |
| commit | 823806ff6bd63f92644a5330cf0c3b68fac25ffd (patch) | |
| tree | 626dd2e694f7591736c91d706ada528783b759cc /arch/x86/pci/mrst.c | |
| parent | 8ed3087280ee8c527b7090887e333761a9c75474 (diff) | |
x86/mrst/pci: avoid SoC fixups on non-SoC platforms
The PCI fixups get executed based upon whether they are linked in. We need
to avoid executing them if we boot a dual SoC/PC type kernel on a PC class
system.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/pci/mrst.c')
| -rw-r--r-- | arch/x86/pci/mrst.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c index c5e81a4d7c1e..140942f66b31 100644 --- a/arch/x86/pci/mrst.c +++ b/arch/x86/pci/mrst.c @@ -43,6 +43,8 @@ #define PCI_FIXED_BAR_4_SIZE 0x14 #define PCI_FIXED_BAR_5_SIZE 0x1c +static int pci_soc_mode = 0; + /** * fixed_bar_cap - return the offset of the fixed BAR cap if found * @bus: PCI bus @@ -233,10 +235,11 @@ struct pci_ops pci_mrst_ops = { */ int __init pci_mrst_init(void) { - printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n"); + printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n"); pci_mmcfg_late_init(); pcibios_enable_irq = mrst_pci_irq_enable; pci_root_ops = pci_mrst_ops; + pci_soc_mode = 1; /* Continue with standard init */ return 1; } @@ -246,6 +249,10 @@ int __init pci_mrst_init(void) */ static void __devinit pci_d3delay_fixup(struct pci_dev *dev) { + /* PCI fixups are effectively decided compile time. If we have a dual + SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */ + if (!pci_soc_mode) + return; /* true pci devices in lincroft should allow type 1 access, the rest * are langwell fake pci devices. */ @@ -274,6 +281,9 @@ static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev) u32 size; int i; + if (!pci_soc_mode) + return; + /* Must have extended configuration space */ if (dev->cfg_size < PCIE_CAP_OFFSET + 4) return; |