diff options
| author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2014-01-09 18:14:32 -0800 |
|---|---|---|
| committer | Seema Khowala <seemaj@nvidia.com> | 2014-02-09 10:28:10 -0800 |
| commit | 35f21ec543e53a43bf3a90b4f26915eeec692a0c (patch) | |
| tree | 3b9e48caaf8b9673c42b0cd5f5dfebc029c11b19 /arch | |
| parent | 6056d56ba1a70f53a37ea1eaee2fd169d4a82d52 (diff) | |
ARM: T132: dvfs: Update dfll request ratio for 1st post silicon table
DFLL VCO will run at twice the requested frequency and clk divider
will be set to 2 to match the requested value. This change to be
removed after proper DFLL settings are available for T132.
Bug 1440923
Change-Id: I89c49d11677831677a385a0c4ef2d9bee4761693
Reviewed-on: http://git-master/r/354033
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/361711
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 8 |
2 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index 7b37961db6dc..5a49dff7e955 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -1226,7 +1226,7 @@ static void tegra13_cpu_clk_init(struct clk *c) */ val = clk13_readl(c->reg + SUPER_CLK_DIVIDER); BUG_ON(val & SUPER_CLOCK_DIV_U71_MASK); - val = 0; + val = 0x00020000; clk13_writel(val, c->reg + SUPER_CLK_DIVIDER); } else @@ -1261,7 +1261,7 @@ static int tegra13_cpu_clk_set_parent(struct clk *c, struct clk *p) if (c->flags & DIV_U71) { /* Make sure 7.1 divider is 1:1 */ u32 div = clk13_readl(c->reg + SUPER_CLK_DIVIDER); - BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK); + /* BUG_ON(div & SUPER_CLOCK_DIV_U71_MASK); */ } if (c->refcnt) @@ -4337,10 +4337,17 @@ static void tegra12_dfll_clk_disable(struct clk *c) static int tegra12_dfll_clk_set_rate(struct clk *c, unsigned long rate) { +#ifdef CONFIG_ARCH_TEGRA_13x_SOC + int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate*2); + + if (!ret) + c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs)/2; +#else int ret = tegra_cl_dvfs_request_rate(c->u.dfll.cl_dvfs, rate); if (!ret) c->rate = tegra_cl_dvfs_request_get(c->u.dfll.cl_dvfs); +#endif return ret; } @@ -7378,9 +7385,9 @@ static struct clk_mux_sel mux_cclk_g[] = { { .input = &tegra_clk_sclk, .value = 6}, { .input = &tegra_clk_m, .value = 7}, { .input = &tegra_pll_x, .value = 8}, - /* { .input = , .value = 9}, - High jitter DFLL */ + { .input = &tegra_dfll_cpu, .value = 9}, /* - High jitter DFLL */ /* { .input = , .value = 14}, - High jitter PLLX */ - { .input = &tegra_dfll_cpu, .value = 15}, + /* { .input = &tegra_dfll_cpu, .value = 15}, */ { 0, 0}, }; diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index 529d8b3b8120..6bdb8a7e7d4e 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -2555,11 +2555,19 @@ int tegra_cl_dvfs_request_rate(struct tegra_cl_dvfs *cld, unsigned long rate) rate = GET_REQUEST_RATE(val, cld->ref_rate); /* Find safe voltage for requested rate */ +#ifdef CONFIG_ARCH_TEGRA_13x_SOC + if (find_safe_output(cld, rate/2, &req.output)) { + pr_err("%s: Failed to find safe output for rate %lu\n", + __func__, rate); + return -EINVAL; + } +#else if (find_safe_output(cld, rate, &req.output)) { pr_err("%s: Failed to find safe output for rate %lu\n", __func__, rate); return -EINVAL; } +#endif req.cap = req.output; /* |