diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2014-01-22 15:27:05 -0700 |
|---|---|---|
| committer | Troy Kisky <troy.kisky@boundarydevices.com> | 2014-04-24 18:59:30 -0700 |
| commit | 34f9895be8ce19db4d832f89b03a0d74a1ee981f (patch) | |
| tree | 4ca052897b15460d3c6cb9881f3f60efae6fa647 /arch | |
| parent | 32991aa1ef4a139c3b10a71120f0f82c3f2f4eea (diff) | |
imx6q: allow 1GHZ for TO1.0
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/mach-imx6q.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 5fb11af5643d..1cf7a53b73d1 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -357,17 +357,23 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) */ val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; + val &= 3; if (cpu_is_imx6q()) { - if ((val & 0x3) < OCOTP_CFG3_SPEED_1P2GHZ) + if (!val) { + /* fuses not set for IMX_CHIP_REVISION_1_0 */ + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) + val = OCOTP_CFG3_SPEED_1GHZ; + } + if (val < OCOTP_CFG3_SPEED_1P2GHZ) if (opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); } - if ((val & 0x3) < OCOTP_CFG3_SPEED_1GHZ) + if (val < OCOTP_CFG3_SPEED_1GHZ) if (opp_disable(cpu_dev, 996000000)) pr_warn("failed to disable 1 GHz OPP\n"); if (cpu_is_imx6q()) { - if ((val & 0x3) < OCOTP_CFG3_SPEED_850MHZ || - (val & 0x3) == OCOTP_CFG3_SPEED_1GHZ) + if (val < OCOTP_CFG3_SPEED_850MHZ || + val == OCOTP_CFG3_SPEED_1GHZ) if (opp_disable(cpu_dev, 852000000)) pr_warn("failed to disable 850 MHz OPP\n"); } |