diff options
| author | Anson Huang <b20788@freescale.com> | 2015-07-16 21:11:28 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-07-22 18:24:12 +0800 |
| commit | 63ebf415bb3eda142468d1cf2e7d2b9bcca60e57 (patch) | |
| tree | 4f351f13ef74ba9b0de9785261b36318a720f880 /arch | |
| parent | d345fd34b4eeec5222ed3115ebf8fa88f92da8bf (diff) | |
MLK-11249-3 ARM: imx: improve i.mx6ul's low power idle setting
For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts.
However, the previous setting of RBC counter is 1, which is ~30us,
but the hardware design recommend a ~90us is required during ARM
core power down, so we update the RBC counter value to 4(~120us) here.
Previous delay loop to make sure RBC is actually enabled, 3us is
needed, but the loop value assume ARM is running @1GHz, but actually
ARM is running @24MHz now, so we need to update the loop value
according to ARM speed.
The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during
low power idle, so the total latency of cpuidle exit should be
updated accordingly.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 6d6dc82a4888f936cd2fde968e4f4854c2181eb8)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/cpuidle-imx6ul.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx6ul_low_power_idle.S | 10 |
2 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/cpuidle-imx6ul.c b/arch/arm/mach-imx/cpuidle-imx6ul.c index 13a2755d27cc..e54802e3a55b 100644 --- a/arch/arm/mach-imx/cpuidle-imx6ul.c +++ b/arch/arm/mach-imx/cpuidle-imx6ul.c @@ -131,12 +131,12 @@ static struct cpuidle_driver imx6ul_cpuidle_driver = { /* LOW POWER IDLE */ { /* - * RBC 31us + ARM gating 93us + RBC clear 65us + * RBC 130us + ARM gating 1370us + RBC clear 65us * + PLL2 relock 450us and some margin, here set - * it to 650us. + * it to 2100us. */ - .exit_latency = 650, - .target_residency = 1000, + .exit_latency = 2100, + .target_residency = 2500, .flags = CPUIDLE_FLAG_TIME_VALID, .enter = imx6ul_enter_wait, .name = "LOW-POWER-IDLE", diff --git a/arch/arm/mach-imx/imx6ul_low_power_idle.S b/arch/arm/mach-imx/imx6ul_low_power_idle.S index bd312d83dcc1..5db724e251e6 100644 --- a/arch/arm/mach-imx/imx6ul_low_power_idle.S +++ b/arch/arm/mach-imx/imx6ul_low_power_idle.S @@ -691,14 +691,14 @@ save_and_set_mmdc_io_lpm: /* * enable the RBC bypass counter here * to hold off the interrupts. RBC counter - * = 1 (30us). With this setting, the latency + * = 4 (120us). With this setting, the latency * from wakeup interrupt to ARM power up - * is ~40uS. + * is ~130uS. */ ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] ldr r3, [r10, #MX6Q_CCM_CCR] bic r3, r3, #(0x3f << 21) - orr r3, r3, #(0x1 << 21) + orr r3, r3, #(0x4 << 21) str r3, [r10, #MX6Q_CCM_CCR] /* enable the counter. */ @@ -715,7 +715,7 @@ save_and_set_mmdc_io_lpm: /* * now delay for a short while (3usec) - * ARM is at 1GHz at this point + * ARM is at 24MHz at this point * so a short loop should be enough. * this delay is required to ensure that * the RBC counter can start counting in @@ -723,7 +723,7 @@ save_and_set_mmdc_io_lpm: * or in case an interrupt arrives just * as ARM is about to assert DSM_request. */ - ldr r4, =2000 + ldr r4, =50 rbc_loop: subs r4, r4, #0x1 bne rbc_loop |