diff options
| author | Will Deacon <will.deacon@arm.com> | 2015-03-17 12:15:02 +0000 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2015-10-07 10:12:14 -0400 |
| commit | be9d2b0eaf8d401979bbbb9e353beecc4ac8650a (patch) | |
| tree | 4f914e1a367ab4b342d84a4d80444a6d11009681 /arch | |
| parent | dbb4b0e5a9ad6ec3221bcea438e585d6410df22d (diff) | |
arm64: errata: add module build workaround for erratum #843419
[ Upstream commit df057cc7b4fa59e9b55f07ffdb6c62bf02e99a00 ]
Cortex-A53 processors <= r0p4 are affected by erratum #843419 which can
lead to a memory access using an incorrect address in certain sequences
headed by an ADRP instruction.
There is a linker fix to generate veneers for ADRP instructions, but
this doesn't work for kernel modules which are built as unlinked ELF
objects.
This patch adds a new config option for the erratum which, when enabled,
builds kernel modules with the mcmodel=large flag. This uses absolute
addressing for all kernel symbols, thereby removing the use of ADRP as
a PC-relative form of addressing. The ADRP relocs are removed from the
module loader so that we fail to load any potentially affected modules.
Cc: <stable@vger.kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/Kconfig | 16 | ||||
| -rw-r--r-- | arch/arm64/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm64/kernel/module.c | 2 |
3 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 88d6f7fae840..00b9c4870230 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -579,6 +579,22 @@ source "drivers/cpuidle/Kconfig" source "drivers/cpufreq/Kconfig" +config ARM64_ERRATUM_843419 + bool "Cortex-A53: 843419: A load or store might access an incorrect address" + depends on MODULES + default y + help + This option builds kernel modules using the large memory model in + order to avoid the use of the ADRP instruction, which can cause + a subsequent memory access to use an incorrect address on Cortex-A53 + parts up to r0p4. + + Note that the kernel itself must be linked with a version of ld + which fixes potentially affected ADRP instructions through the + use of veneers. + + If unsure, say Y. + endmenu source "net/Kconfig" diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 20901ffed182..e7391aef5433 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -32,6 +32,10 @@ endif CHECKFLAGS += -D__aarch64__ +ifeq ($(CONFIG_ARM64_ERRATUM_843419), y) +CFLAGS_MODULE += -mcmodel=large +endif + # Default value head-y := arch/arm64/kernel/head.o diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index 1eb1cc955139..e366329d96d8 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -330,12 +330,14 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21, AARCH64_INSN_IMM_ADR); break; +#ifndef CONFIG_ARM64_ERRATUM_843419 case R_AARCH64_ADR_PREL_PG_HI21_NC: overflow_check = false; case R_AARCH64_ADR_PREL_PG_HI21: ovf = reloc_insn_imm(RELOC_OP_PAGE, loc, val, 12, 21, AARCH64_INSN_IMM_ADR); break; +#endif case R_AARCH64_ADD_ABS_LO12_NC: case R_AARCH64_LDST8_ABS_LO12_NC: overflow_check = false; |