diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-05-25 10:00:33 +0530 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-26 11:46:53 -0700 |
| commit | 541dcf9b30dd2f66a344ec3f9bab84f84f3008b4 (patch) | |
| tree | af9d7a27dc19c2f3e2e8327bc4af05ab5726491a /arch | |
| parent | 838291a96a52a9c57ca000629055442a7be4e4d3 (diff) | |
ARM: tegra: clocks: init shared clk after sku limit
shared clock rate is dependent on its parent max rate. Parent's max rate
get updated in sku limit init depending on the sku value. Hence initialize
shared clocks after sku limits are applied.
Bug 821534
Change-Id: I505b03bc03702c198f07f36437b2e9f3fc8e50cb
Reviewed-on: http://git-master/r/29803
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 796423dd61c7..46d9c684c9ed 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2072,7 +2072,7 @@ static struct clk tegra_clk_emc = { .parent = _parent, \ } -struct clk tegra_list_clks[] = { +struct clk tegra_list_periph_clks[] = { PERIPH_CLK("apbdma", "apbdma", "apbdma", 34, 0, 0x31E, 26000000, mux_clk_m, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), @@ -2137,7 +2137,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 0x31E, 150000000, mux_clk_m, 0), /* same frequency as VI */ PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 0x31E, 150000000, mux_clk_m, PERIPH_NO_RESET), PERIPH_CLK("stat_mon", "tegra-stat-mon", NULL, 37, 0, 0x31E, 26000000, mux_clk_m, 0), +}; +struct clk tegra_list_shared_clks[] = { SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("usbd.sclk", "fsl-tegra-udc", "sclk", &tegra_clk_virtual_sclk), @@ -2318,8 +2320,8 @@ void __init tegra_soc_init_clocks(void) for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) tegra2_init_one_clock(tegra_ptr_clks[i]); - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra2_init_one_clock(&tegra_list_clks[i]); + for (i = 0; i < ARRAY_SIZE(tegra_list_periph_clks); i++) + tegra2_init_one_clock(&tegra_list_periph_clks[i]); for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); @@ -2335,6 +2337,9 @@ void __init tegra_soc_init_clocks(void) init_audio_sync_clock_mux(); tegra2_init_sku_limits(); + + for (i = 0; i < ARRAY_SIZE(tegra_list_shared_clks); i++) + tegra2_init_one_clock(&tegra_list_shared_clks[i]); } #ifdef CONFIG_CPU_FREQ |