diff options
| author | Anson Huang <b20788@freescale.com> | 2015-08-20 20:25:28 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:01:41 -0600 |
| commit | 1419198781a03857f4f394f180c505e57a4ae64f (patch) | |
| tree | d3ab1aaf0b62cfed47333704e595036ad7fd08aa /arch | |
| parent | fe42c755539326a69f0f0b397bb1daa23dd24480 (diff) | |
MLK-11387-3 ARM: imx: update ddr freq scale setting on imx7d
To pass stress test in high temperature environment,
according to design team's suggestion, need to adjust
ddr phy setting for LPDDR3.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/lpddr3_freq_imx.S | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/lpddr3_freq_imx.S b/arch/arm/mach-imx/lpddr3_freq_imx.S index 0ced151a01c7..9357627d8c57 100644 --- a/arch/arm/mach-imx/lpddr3_freq_imx.S +++ b/arch/arm/mach-imx/lpddr3_freq_imx.S @@ -15,6 +15,7 @@ #include <linux/linkage.h> #include "hardware.h" +#define DDRC_MSTR 0x0 #define DDRC_STAT 0x4 #define DDRC_PWRCTL 0x30 #define DDRC_DBG1 0x304 @@ -36,6 +37,7 @@ #define DDRPHY_OFFSETW_CON0 0x30 #define DDRPHY_OFFSETW_CON1 0x34 #define DDRPHY_OFFSETW_CON2 0x38 +#define DDRPHY_RFSHTMG 0x64 #define DDRPHY_CA_DSKEW_CON0 0x7c #define DDRPHY_CA_DSKEW_CON1 0x80 #define DDRPHY_CA_DSKEW_CON2 0x84 @@ -118,8 +120,22 @@ .macro switch_to_below_100m + /* LPDDR2 and LPDDR3 has different setting */ + ldr r8, [r4, #DDRC_MSTR] + ands r8, r8, #0x4 + bne 9f + + /* LPDDR3 */ + ldr r7, =0x00000100 + str r7, [r5, #DDRPHY_PHY_CON1] + b 10f +9: + /* LPDDR2 */ ldr r7, =0x10010100 str r7, [r5, #DDRPHY_PHY_CON1] +10: + ldr r7, =0x00020038 + str r7, [r5, #DDRPHY_RFSHTMG] ldr r6, =24000000 cmp r0, r6 @@ -180,6 +196,9 @@ ldr r7, =0x10210100 str r7, [r5, #DDRPHY_PHY_CON1] + ldr r7, =0x00200038 + str r7, [r5, #DDRPHY_RFSHTMG] + /* dram root set to from dram main, div by 2 */ ldr r7, =0x10000001 ldr r8, =0x9880 |