diff options
author | Philippe Schenker <philippe.schenker@toradex.com> | 2019-07-12 10:28:36 +0200 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-12 11:06:01 +0100 |
commit | 294497dc9b04534df1719d56d3d48dedd8b53c5c (patch) | |
tree | 95282fbac29bfe7ed85bd69d4acd120faf269f91 /arch | |
parent | 251c7ce953f605e44a1fea3e750344fe52e5b06e (diff) |
ARM64: dts: colibri-imx8x: Move entries from eval to SoM-level
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'arch')
5 files changed, 59 insertions, 112 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts index b5c616a6b75c..c03a4083082e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts @@ -16,11 +16,6 @@ /* DSI/LVDS port 0 */ &i2c0_mipi_lvds0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; - clock-frequency = <100000>; status = "okay"; #ifndef DSI_TO_HDMI_V10 @@ -163,7 +158,6 @@ }; &mipi_dsi1 { - pwr-delay = <10>; status = "okay"; }; @@ -176,24 +170,3 @@ }; }; }; - -&ldb2_phy { - status = "disabled"; -}; - -&ldb2 { - status = "disabled"; -}; - -&mipi_dsi_phy2 { - status = "disabled"; -}; - -&mipi_dsi2 { - pwr-delay = <10>; - status = "disabled "; -}; - -&mipi_dsi_bridge2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts index a139577986d3..744fe282983a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -155,8 +155,7 @@ clock-frequency = <100000>; status = "disabled"; }; - -/* On-module MIPI CSI I2C accessible via FFC (X3) */ +/* On-module MIPI CSI I2C accessible on FFC (X3) */ &i2c0_mipi_lvds1 { status = "okay"; @@ -183,11 +182,11 @@ }; }; -&ldb1_phy { +&ldb1 { status = "disabled"; }; -&ldb1 { +&ldb1_phy { status = "disabled"; }; @@ -217,19 +216,6 @@ }; }; -&mipi_dsi_phy1 { - status = "disabled"; -}; - -&mipi_dsi1 { - pwr-delay = <10>; - status = "disabled"; -}; - -&mipi_dsi_bridge1 { - status = "disabled"; -}; - &i2c1 { status = "okay"; @@ -240,16 +226,6 @@ }; }; -/* DSI/LVDS port 1 */ -&i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; - clock-frequency = <100000>; - status = "disabled"; -}; - &ldb2_phy { status = "disabled"; }; @@ -264,19 +240,6 @@ }; }; -&mipi_dsi_phy2 { - status = "disabled"; -}; - -&mipi_dsi2 { - pwr-delay = <10>; - status = "disabled "; -}; - -&mipi_dsi_bridge2 { - status = "disabled"; -}; - &pwm_adma_lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_a>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts index a7aeb33a5ea4..ad8fa0d35557 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts @@ -47,16 +47,6 @@ }; }; -/* DSI/LVDS port 0 */ -&i2c0_mipi_lvds0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; - clock-frequency = <100000>; - status = "disabled"; -}; - &ldb1_phy { status = "okay"; }; @@ -86,7 +76,6 @@ }; &mipi_dsi1 { - pwr-delay = <10>; status = "okay"; }; @@ -94,16 +83,6 @@ status = "disabled"; }; -/* DSI/LVDS port 1 */ -&i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; - clock-frequency = <100000>; - status = "disabled"; -}; - &ldb2_phy { status = "okay"; }; @@ -117,11 +96,9 @@ }; &mipi_dsi2 { - pwr-delay = <10>; status = "okay"; }; &mipi_dsi_bridge2 { status = "disabled"; }; - diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts index 4e243d04894a..53b6720b1241 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts @@ -54,16 +54,6 @@ }; }; -/* DSI/LVDS port 0 */ -&i2c0_mipi_lvds0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; - clock-frequency = <100000>; - status = "disabled"; -}; - &ldb1_phy { status = "okay"; }; @@ -91,7 +81,6 @@ }; &mipi_dsi1 { - pwr-delay = <10>; status = "okay"; }; @@ -99,13 +88,8 @@ status = "disabled"; }; -/* DSI/LVDS port 1 */ +/* On-module MIPI DSI accessible on FFC (X2) */ &i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; - clock-frequency = <100000>; status = "disabled"; }; @@ -122,7 +106,6 @@ }; &mipi_dsi2 { - pwr-delay = <10>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi index ceb754eca674..1ce4a3d3386b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi @@ -246,14 +246,22 @@ }; }; -/* On-module MIPI CSI I2C accessible via FFC (X3) */ +/* On-module MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; +}; + +/* On-module MIPI CSI accessible on FFC (X3) */ &i2c0_mipi_lvds1 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_mipi_csi>; - status = "disabled"; }; /* Colibri I2C */ @@ -684,7 +692,7 @@ >; }; - /* MIPI DSI0 I2C on FFC (X2) */ + /* On-module MIPI DSI I2C accessible on FFC (X2) */ pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ @@ -692,7 +700,7 @@ >; }; - /* On-module MIPI CSI I2C accessible via FFC (X3) */ + /* On-module MIPI CSI I2C accessible on FFC (X3) */ pinctrl_i2c0_mipi_csi: mipi_csi_i2c0_grp { fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ @@ -734,6 +742,22 @@ status = "okay"; }; +&ldb1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + /* Colibri SPI */ &lpspi2 { #address-cells = <1>; @@ -774,6 +798,33 @@ status = "disabled"; }; +&mipi_dsi1 { + pwr-delay = <10>; + status = "disabled"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +&mipi_dsi_phy1 { + status = "disabled"; +}; + +&mipi_dsi2 { + pwr-delay = <10>; + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + + /* On-module PCIe for wifi */ &pcieb{ pinctrl-names = "default"; |