arm: tegra: support for FIQ debugger with secure OS

Most of the set up for the debugger is done by the secure
OS, but the kernel setup that needs to be done is done here.

Use the following config options to enable the debugger -

CONFIG_FIQ=y
CONFIG_TEGRA_FIQ_DEBUGGER=y
CONFIG_FIQ_GLUE=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_TEGRA_WATCHDOG=y
CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE=y

Bug 1326082

Original-author: Hyung Taek Ryoo <hryoo@nvidia.com>

Change-Id: If1a5dd4f158530dea6c0455ead74a8eeaa226163
Reviewed-on: http://git-master/r/#/c/261217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/289165

4 files changed, 37 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/board-ardbeg.c b/arch/arm/mach-tegra/board-ardbeg.c
index 70ab7b5d4c4c..cfda8d5391cf 100644
--- a/arch/arm/mach-tegra/board-ardbeg.c
+++ b/arch/arm/mach-tegra/board-ardbeg.c
@@ -434,6 +434,9 @@ static struct platform_device *ardbeg_devices[] __initdata = {
 	&tegra_pmu_device,
 	&tegra_rtc_device,
 	&tegra_udc_device,
+#if defined(CONFIG_TEGRA_WATCHDOG)
+	&tegra_wdt0_device,
+#endif
 #if defined(CONFIG_TEGRA_AVP)
 	&tegra_avp_device,
 #endif
@@ -1098,7 +1101,6 @@ static void __init tegra_ardbeg_late_init(void)
 	ardbeg_setup_bluedroid_pm();
 	tegra_register_fuse();
 	bonaire_sata_init();
-	tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
 }
 
 static void __init ardbeg_ramconsole_reserve(unsigned long size)
diff --git a/arch/arm/mach-tegra/board-loki.c b/arch/arm/mach-tegra/board-loki.c
index ecfc61bd0ccf..c81c55819bcf 100644
--- a/arch/arm/mach-tegra/board-loki.c
+++ b/arch/arm/mach-tegra/board-loki.c
@@ -302,6 +302,9 @@ static struct platform_device *loki_devices[] __initdata = {
 	&tegra_pmu_device,
 	&tegra_rtc_device,
 	&tegra_udc_device,
+#if defined(CONFIG_TEGRA_WATCHDOG)
+	&tegra_wdt0_device,
+#endif
 #if defined(CONFIG_TEGRA_AVP)
 	&tegra_avp_device,
 #endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 35f5793d29ee..bc2cee0800e0 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -2424,6 +2424,11 @@ static struct resource tegra_wdt_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[2] = {
+		.start	= TEGRA_PMC_BASE,
+		.end	= TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[3] = {
 		.start	= INT_TMR1,
 		.end	= INT_TMR1,
 		.flags	= IORESOURCE_IRQ,
@@ -2449,18 +2454,36 @@ static struct resource tegra_wdt0_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[2] = {
+		.start	= TEGRA_PMC_BASE,
+		.end	= TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[3] = {
 		.start	= INT_WDT_CPU,
 		.end	= INT_WDT_CPU,
 		.flags	= IORESOURCE_IRQ,
 	},
 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
-	[3] = {
+	[4] = {
 		.start	= TEGRA_QUATERNARY_ICTLR_BASE,
 		.end	= TEGRA_QUATERNARY_ICTLR_BASE + \
 				TEGRA_QUATERNARY_ICTLR_SIZE -1,
 		.flags	= IORESOURCE_MEM,
 	},
 #endif
+#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \
+	defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
+	[5] = {
+		.start  = TEGRA_WDT4_BASE,
+		.end    = TEGRA_WDT4_BASE + TEGRA_WDT4_SIZE - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+	[6] = {
+		.start  = INT_WDT_AVP,
+		.end    = INT_WDT_AVP,
+		.flags  = IORESOURCE_IRQ,
+	},
+#endif
 };
 
 struct platform_device tegra_wdt0_device = {
diff --git a/arch/arm/mach-tegra/fiq.c b/arch/arm/mach-tegra/fiq.c
index c4219dab8476..4f650ac6ea09 100644
--- a/arch/arm/mach-tegra/fiq.c
+++ b/arch/arm/mach-tegra/fiq.c
@@ -1,9 +1,11 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *	Brian Swetland <swetland@google.com>
  *	Iliyan Malchev <malchev@google.com>
+ *	Lucas Dai <lucasd@nvidia.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -81,7 +83,12 @@ static void tegra_fiq_unmask(struct irq_data *d)
 
 void tegra_fiq_enable(int irq)
 {
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
+	defined(CONFIG_ARCH_TEGRA_2x_SOC)
 	void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100);
+#else
+	void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x2000);
+#endif
 	/* enable FIQ */
 	u32 val = readl(base + GIC_CPU_CTRL);
 	val &= ~8; /* pass FIQs through */