diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2017-07-20 13:55:14 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | a4e698f1c665610bc6cbfa4b0e231a83b518cf6d (patch) | |
| tree | f792215a34fd80e4194b82ad56087d2e051b3b19 /arch | |
| parent | 0170ff5cee54976f302f9b1f713840699da24237 (diff) | |
MLK-16038 ARM: dts: fsl-imx8mq-evk: improve the usdhc I/O drive strength
Some normal high-speed SD card may meet some CRC error on imx8mq-evk
board, so improve the default usdhc I/O drive strength to fix this.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts index eee97e8a508d..099b56be1b09 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts @@ -160,17 +160,17 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x81 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc1 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc1 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc1 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc1 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc1 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc1 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc1 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc1 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc1 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x81 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 >; }; @@ -218,12 +218,12 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x81 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc1 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc1 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc1 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc1 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc1 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 >; }; |