diff options
| author | Xianzhong <b07117@freescale.com> | 2012-08-03 00:50:19 +0800 |
|---|---|---|
| committer | Xianzhong <b07117@freescale.com> | 2012-08-03 18:56:59 +0800 |
| commit | b60d26819d57d14cb174576c561a2f4e17828dca (patch) | |
| tree | d9ab44b83e8a4fc4fadd727f20a744f0928df899 /arch | |
| parent | 76f691466a56fc235d4f4e138195dc78a5823c37 (diff) | |
ENGR00219193 improve gpu3d core clock to 528M
The original 528M setting is invalid and become 396M actually,
Change gpu3d core clock parent to 594_PFD to enable 528M setting.
Benchmark performance are improved with clock change on i.MX6DL:
Basemark2: 5.85 --> 7.66
Nenamark2: 23.7 --> 27.4
Quadrant 3d: 2186 --> 2270
Signed-off-by: Xianzhong <b07117@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 4d98b2680672..61cf37c9a4f8 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -5354,9 +5354,11 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, */ clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M); clk_set_rate(&gpu3d_shader_clk, 594000000); - clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]); - clk_set_rate(&gpu3d_core_clk[0], 528000000); if (cpu_is_mx6dl()) { + /*for mx6dl, change gpu3d core clk parant to 594_PFD */ + clk_set_parent(&gpu3d_core_clk[0], &pll2_pfd_594M); + clk_set_rate(&gpu3d_core_clk[0], 594000000); + /*on mx6dl, 2d core clock sources from 3d shader core clock*/ clk_set_parent(&gpu2d_core_clk[0], &gpu3d_shader_clk); /* on mx6dl gpu3d_axi_clk source from mmdc0 directly */ @@ -5369,6 +5371,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&ipu2_clk, &pll2_pfd_400M); clk_set_rate(&ipu2_clk, 200000000); } else if (cpu_is_mx6q()) { + clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]); + clk_set_rate(&gpu3d_core_clk[0], 528000000); clk_set_parent(&ipu2_clk, &mmdc_ch0_axi_clk[0]); clk_set_parent(&ipu1_clk, &mmdc_ch0_axi_clk[0]); } |