diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-07-21 17:30:52 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | be15156543fd09839778b7776a85c3a1353021d4 (patch) | |
| tree | a8ec849bbbc1d435be50bde50f8f85490c76b0ca /arch | |
| parent | b4bbc9f01133860e1ee24e30c5a72b09c58b7f4d (diff) | |
MLK-16055 arm64: dts: freescale: imx8mq: enable power domain support
Assign i.MX8MQ power domain id to each module to enable
power domain control for runtime power management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi index 6cf885eb51a5..86ac4c195e89 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi @@ -331,6 +331,7 @@ phy-ref-clkfreq = <27000000>; data-lanes-num = <4>; max-data-rate = <800000000>; + power-domains = <&power 0>; status = "disabled"; }; @@ -510,6 +511,7 @@ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <800000000>; + power-domains = <&power 2>; status = "disabled"; }; @@ -524,6 +526,7 @@ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <800000000>; + power-domains = <&power 3>; status = "disabled"; }; @@ -715,6 +718,7 @@ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI_SRC>, <&clk IMX8MQ_CLK_GPU_AHB_SRC>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>; + power-domains = <&power 4>; status = "disabled"; }; @@ -774,6 +778,7 @@ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1_SRC>, <&clk IMX8MQ_CLK_VPU_G2_SRC>, <&clk IMX8MQ_CLK_VPU_BUS_SRC>; assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&power 5>; status = "disabled"; }; @@ -843,6 +848,7 @@ clock-names = "pcie", "pcie_bus", "pcie_phy"; fsl,max-link-speed = <2>; ctrl-id = <0>; + power-domains = <&power 1>; status = "disabled"; }; @@ -870,6 +876,7 @@ clock-names = "pcie", "pcie_bus", "pcie_phy"; fsl,max-link-speed = <2>; ctrl-id = <1>; + power-domains = <&power 10>; status = "disabled"; }; }; |