diff options
| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-01-27 17:48:20 -0600 |
|---|---|---|
| committer | Adrian Alonso <adrian.alonso@nxp.com> | 2016-02-24 17:16:49 -0600 |
| commit | d5aff938dc30de9e6469a408ec403307509b78f8 (patch) | |
| tree | bb1d8e8ec715b2b67600865fa123545664499276 /arch | |
| parent | 7a11789d1330b54fd916e1db94616f2367d90828 (diff) | |
MLK-12399: ARM: imx: imx6q: lpddr2 busfreq audio operation support
Add 100Mhz (HIGH_AUDIO_CLK) bus frequency support for imx6q lpddr2 targets
On HIGH_AUDIO_CLK busfreq request source dram mmdc clock root from
pll2_pfd2_div_2 to generate 100Mhz operation frequency.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry-picked from commit 5bc118112b36b72ed6b1e75a3760c371b486abec)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/busfreq-imx.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-imx/lpddr2_freq_imx6q.S | 74 |
2 files changed, 75 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c index 7803ea44d3d5..39fe400a48e2 100644 --- a/arch/arm/mach-imx/busfreq-imx.c +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -229,7 +229,7 @@ static void enter_lpm_imx6_smp(void) if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) update_ddr_freq_imx_smp(LOW_AUDIO_CLK); else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) - update_lpddr2_freq(LOW_AUDIO_CLK); + update_lpddr2_freq_smp(HIGH_AUDIO_CLK); /* Make sure periph clk's parent also got updated */ imx_clk_set_parent(periph_clk2_sel_clk, pll3_clk); imx_clk_set_parent(periph_pre_clk, pll2_200_clk); diff --git a/arch/arm/mach-imx/lpddr2_freq_imx6q.S b/arch/arm/mach-imx/lpddr2_freq_imx6q.S index 0987bad072e5..6bf0db68c4b0 100644 --- a/arch/arm/mach-imx/lpddr2_freq_imx6q.S +++ b/arch/arm/mach-imx/lpddr2_freq_imx6q.S @@ -89,6 +89,72 @@ periph_clk_switch6: .endm + .macro switch_to_100MHz + /* check if periph_clk_sel is already set. */ + ldr r9, [r2, #CCM_CBCDR] + and r9, r9, #(1 << 25) + cmp r9, #(1 << 25) + beq switch_pre_periph_clk_100 + /* + * set the periph_clk to be sourced from PLL2_PFD_200M + * change periph_clk to be sourced from pll3_clk. + * ensure PLL3 is the source and set the divider to 1. + */ + ldr r9, [r2, #CCM_CBCMR] + bic r9, r9, #(0x3 << 12) + str r9, [r2, #CCM_CBCMR] + + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(0x38 << 24) + str r9, [r2, #CCM_CBCDR] + + /* now switch periph_clk to pll3_main_clk. */ + ldr r9, [r2, #CCM_CBCDR] + orr r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + +periph_clk_switch_100: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne periph_clk_switch_100 + +switch_pre_periph_clk_100: + /* now switch pre_periph_clk to PFD_200MHz. */ + ldr r9, [r2, #CCM_CBCMR] + orr r9, r9, #(0xc << 16) + str r9, [r2, #CCM_CBCMR] + + /* set the MMDC_DIV=2, AXI_DIV=4, AHB_DIV=8 */ + ldr r9, [r2, #CCM_CBCDR] + ldr r6, =0x3f1f00 + bic r9, r9, r6 + orr r9, r9, #(0x8 << 16) + orr r9, r9, #(0x3 << 16) + + /* + * if changing AHB divider remember to change + * the IPGPER divider too below. + */ + orr r9, r9, #0x1d00 + str r9, [r2, #CCM_CBCDR] + +wait_div_update_100: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne wait_div_update_100 + + /* now switch periph_clk back. */ + ldr r9, [r2, #CCM_CBCDR] + bic r9, r9, #(1 << 25) + str r9, [r2, #CCM_CBCDR] + +periph_clk_switch2: + ldr r9, [r2, #CCM_CDHIPR] + cmp r9, #0 + bne periph_clk_switch2 + + .endm + .macro switch_to_24MHz /* * change the freq now try setting DDR to 24MHz. @@ -544,6 +610,10 @@ set_ddr_mu_above_100: cmp r0, r10 beq set_to_24MHz + ldr r10, =100000000 + cmp r0, r10 + beq set_to_100MHz + ldr r10, =400000000 cmp r0, r10 switch_to_400MHz @@ -554,6 +624,10 @@ set_to_24MHz: switch_to_24MHZ_from_pll2 */ switch_to_24MHz + b done + +set_to_100MHz: + switch_to_100MHz done: |