tegra: Clean up conditionals and whitespace

Change-Id: I6855c9cfcfaf2646569fcad5ae0090eb47f11dff Reviewed-on: http://git-master/r/2963 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
author: Scott Williams <scwilliams@nvidia.com> 2010-06-21 16:51:30 -0700
committer: Gary King <gking@nvidia.com> 2010-06-22 09:50:46 -0700
commit: 7965e62aa8528e621a1d1c6503de33b91826cc98 (patch)
tree: 3b276ffbf4f84a6ef646f214770d7e80be16061c /arch
parent: d81df22941c19ac21e9da751fd8d1835bab9a834 (diff)
20 files changed, 285 insertions, 322 deletions
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S
index d12055533df3..0ddfa5d77215 100644
--- a/arch/arm/mach-tegra/cortex-a9.S
+++ b/arch/arm/mach-tegra/cortex-a9.S
@@ -444,5 +444,3 @@ __reenable_l2x0:
 	str	r3, [r9, #L2X0_CTRL]
 #endif
 	b	__cortex_a9_restore
-
-
diff --git a/arch/arm/mach-tegra/cpufreq.c b/arch/arm/mach-tegra/cpufreq.c
index 149ad936b00c..ae5f0eac734f 100644
--- a/arch/arm/mach-tegra/cpufreq.c
+++ b/arch/arm/mach-tegra/cpufreq.c
@@ -84,7 +84,6 @@ static void tegra_cpufreq_hotplug(NvRmPmRequest req)
 	if (rc)
 		pr_err("%s: error %d servicing hot plug request\n",
 		       __func__, rc);
-	
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -185,7 +184,6 @@ int tegra_start_dvfsd(void) {
 	mutex_unlock(&init_mutex);
 
 	return rc;
-
 }
 
 static int tegra_cpufreq_init_once(void)
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 57fb8f56ef66..fc65c0444ee8 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -228,6 +228,7 @@ __restart_pllx:
 	mov	r0, #0
 	b	__cortex_a9_l2x0_restart
 ENDPROC(__restart_pllx)
+
 /*
  *	__enable_coresite_access
  *
@@ -257,6 +258,7 @@ access:	str	r5, [r6]
 	bhi	access
 	mov	pc, lr
 ENDPROC(__enable_coresite_access)
+
 /*
  *	tegra_lp2_startup
  *
@@ -303,7 +305,7 @@ __tegra_lp2_data:
 	.long	__restart_pllx
 	.size	__tegra_lp2_data, . - __tegra_lp2_data
 
-#ifdef CONFIG_HOTPLUG_CPU
+
 /*
  *	tegra_hotplug_startup
  *
@@ -339,4 +341,3 @@ __tegra_hotplug_data:
 	.long	tegra_pgd_phys
 	.long	__cortex_a9_restore
 	.size	__tegra_hotplug_data, . - __tegra_hotplug_data
-#endif
-\ No newline at end of file
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
index 3f7c8dc10872..7c1600f0e2ac 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux-t2.h
@@ -159,4 +159,3 @@ typedef enum {
 	}
 
 #endif
-
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 7fa0a926cfce..67e0fc48ef6d 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -154,4 +154,3 @@ int tegra_pinmux_get_vddio(tegra_pingroup_t pg);
 void tegra_pinmux_set_vddio_tristate(tegra_vddio_t vddio,
 				     tegra_tristate_t tristate);
 #endif
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index ca63729f2673..96ae3488025e 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -336,7 +336,7 @@ NvRmPrivAp15PllSet(
      *
      * c) PLLD/PLLU miscellaneous register has a unique fields determined based
      *  on the input flags. For other PLLs these fields have different meaning,
-     *  and will be preserved. 
+     *  and will be preserved.
      *
      *  PLLP h/w field definitions will be used in DRF macros to construct
      *  miscellaneous values with common layout. For unique fields PLLD h/w
@@ -846,7 +846,7 @@ PllUhsConfigure(NvRmDeviceHandle hRmDevice, NvRmFreqKHz TargetFreq)
                   CLK_RST_CONTROLLER_OSC_CTRL_0);
     reg = NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, reg);
 
-    // If PLLU is already configured - exit 
+    // If PLLU is already configured - exit
     if (CurrentFreq == s_Ap15UhsPllConfigurations[reg].OutputKHz)
         return;
 
@@ -1011,7 +1011,7 @@ Ap15PllDControl(
     NvRmModuleClockState* pCstate = NULL;
     NV_ASSERT_SUCCESS(NvRmPrivGetClockState(
         hRmDevice, NvRmModuleID_Dsi, &pCinfo, &pCstate));
-    
+
     if (Enable)
     {
         Ap15PllControl(hRmDevice, NvRmClockSource_PllD0, NV_TRUE);
@@ -1187,7 +1187,7 @@ Ap15DisplayClockConfigure(
             (((pCstate->actual_freq * 2 ) + PixelFreq / 2) / PixelFreq) - 2;
         pTvDacState->actual_freq =
             (pCstate->actual_freq * 2 ) / (pTvDacState->Divider + 2);
-        NvRmPrivModuleClockSet(hRmDevice, pTvDacInfo, pTvDacState); 
+        NvRmPrivModuleClockSet(hRmDevice, pTvDacInfo, pTvDacState);
     }
     if (flags & NvRmClockConfig_DisableTvDAC)
     {
@@ -1236,7 +1236,7 @@ NvRmPrivAp15IsModuleClockException(
             /*
              * Reconfigure PLLD to match requested frequency, and update DSI
              * clock state.
-             */ 
+             */
             Ap15PllDConfigure(hRmDevice, PrefFreqList[0]);
             NV_ASSERT((MinFreq <= pCstate->actual_freq) &&
                       (pCstate->actual_freq <= MaxFreq));
@@ -1295,7 +1295,7 @@ NvRmPrivAp15IsModuleClockException(
                 pCstate->actual_freq = (FreqKHz << 1) / (pCstate->Divider + 2);
                 if (NvRmPrivGetExecPlatform(hRmDevice) == ExecPlatform_Fpga)
                 {   // Fake return on FPGA (PLLA is not configurable, anyway)
-                    pCstate->actual_freq = PrefFreqList[0]; 
+                    pCstate->actual_freq = PrefFreqList[0];
                 }
                 NV_ASSERT(pCinfo->Sources[pCstate->SourceClock] ==
                           NvRmClockSource_PllA0);
@@ -1311,7 +1311,7 @@ NvRmPrivAp15IsModuleClockException(
             /*
              * Reconfigure PLLU to match requested frequency, and complete USB
              * clock configuration (PLLU is a single source, no divider)
-             */ 
+             */
             Ap15PllUConfigure(hRmDevice, PrefFreqList[0]);
             pCstate->SourceClock = 0;
             pCstate->Divider = 1;
@@ -1797,7 +1797,7 @@ NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice)
                 s_Ap15EmcConfigSortedTable[i].FbioDqsibDly =
                     pEmcConfigurations[j].EmcFbioDqsibDly +
                     NvRmPrivGetEmcDqsibOffset(hRmDevice);
-                s_Ap15EmcConfigSortedTable[i].FbioQuseDly = 
+                s_Ap15EmcConfigSortedTable[i].FbioQuseDly =
                     pEmcConfigurations[j].EmcFbioQuseDly;
                 s_Ap15EmcConfigSortedTable[i].CoreVoltageMv =
                     pEmcConfigurations[j].EmcCoreVoltageMv;
@@ -1877,7 +1877,7 @@ NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice)
                  * Final CPU clock limit is minimum of the above limits
                  */
                 s_Ap15EmcConfigSortedTable[i].CpuLimitKHz =
-                    (NvU32)NvDiv64(((NvU64)Emc2xKHz * McKHz * 119), 
+                    (NvU32)NvDiv64(((NvU64)Emc2xKHz * McKHz * 119),
                                 (((McKHz << 2) - Emc2xKHz) * 10));
                 reg = NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
                 if (k != 0)
@@ -1894,7 +1894,7 @@ NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice)
         if (s_Ap15EmcConfigSortedTable[i].Emc2xKHz != 0)
             i++;                // Entry found - advance sorting index
         else if (i == 0)
-            break;              // PLLM0 entry not found - abort sorting 
+            break;              // PLLM0 entry not found - abort sorting
 
         Emc2xKHz = PllM0KHz / ((++k) << 1);
         if (Emc2xKHz < NvRmPrivGetSocClockLimits(
@@ -2060,7 +2060,7 @@ NvRmPrivAp15FastClockConfig(NvRmDeviceHandle hRmDevice)
 
     // Now configure both dividers and select the output with highest frequency
     // as a source for the system bus clock; reconfigure MIO as necessary
-    SclkKHz = NV_MAX(PllM1KHz, PllP2KHz); 
+    SclkKHz = NV_MAX(PllM1KHz, PllP2KHz);
     FreqKHz = NvRmPrivGetClockSourceFreq(NvRmClockSource_SystemBus);
     if (FreqKHz < SclkKHz)
     {
@@ -2245,7 +2245,7 @@ Ap15SystemClockSourceFind(
 
     /*
      * 4st and final option - PLLM divider fixed at maximum possible frequency
-     * during initialization. Select PLLP/PLLM divider according to the 
+     * during initialization. Select PLLP/PLLM divider according to the
      * following rule: select the divider with smaller frequency if it is equal
      * or above the target frequency, otherwise select the divider with bigger
      * output frequency.
@@ -2675,7 +2675,7 @@ NvRmPrivAp15DfsVscaleFreqGet(
         {
             if ((s_Ap15EmcConfigSortedTable[i+1].Emc2xKHz == 0) ||
                 (s_Ap15EmcConfigSortedTable[i].CoreVoltageMv <= TargetMv))
-                break;  // exit if found entry or next entry is invalid 
+                break;  // exit if found entry or next entry is invalid
         }
         pDfsKHz->Domains[NvRmDfsClockId_Emc] =
             (s_Ap15EmcConfigSortedTable[i].Emc2xKHz >> 1);
@@ -2684,7 +2684,7 @@ NvRmPrivAp15DfsVscaleFreqGet(
 
     // Binary search for maximum CPU frequency, with source that can be used
     // at target voltage or below
-    Fb = NV_MIN(CpuMaxKHz, f); 
+    Fb = NV_MIN(CpuMaxKHz, f);
     Fa = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
     NV_ASSERT(Fa <= Fb);
     while ((Fb - Fa) > 1000)    // 1MHz resolution
@@ -2701,7 +2701,7 @@ NvRmPrivAp15DfsVscaleFreqGet(
 
     // Binary search for maximum System/Avp frequency, with source that can be used
     // at target voltage or below
-    Fb = SysMaxKHz; 
+    Fb = SysMaxKHz;
     Fa = NvRmPrivGetClockSourceFreq(NvRmClockSource_ClkM);
     NV_ASSERT(Fa <= Fb);
     while ((Fb - Fa) > 1000)    // 1MHz resolution
@@ -2720,6 +2720,3 @@ NvRmPrivAp15DfsVscaleFreqGet(
     pDfsKHz->Domains[NvRmDfsClockId_Apb] = Fa;
     pDfsKHz->Domains[NvRmDfsClockId_Vpipe] = Fa;
 }
-
-/*****************************************************************************/
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c
index 97835ad98399..15b5ec8e7f76 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_misc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -506,6 +506,3 @@ NvRmPrivCheckBondOut( NvRmDeviceHandle hDevice )
         }
     }
 }
-
-/*****************************************************************************/
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c
index 09b1587fb1d1..582d922e7328 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_init.c
@@ -384,7 +384,7 @@ NvRmOpenNew(NvRmDeviceHandle *pHandle)
         }
 
         // WAR for bug 600821
-        if ((rm->ChipId.Id == 0x20) && 
+        if ((rm->ChipId.Id == 0x20) &&
             (rm->ChipId.Major == 0x1) && (rm->ChipId.Minor == 0x2))
         {
             err = NvRmQueryChipUniqueId(rm, sizeof (NvU64), &Uid);
@@ -679,5 +679,3 @@ void NvRmPrivMcErrorMonitorStop( NvRmDeviceHandle rm )
         break;
     }
 }
-
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
index e5da471f42a8..72fda186418d 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_memctrl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -59,8 +59,8 @@ typedef struct ObsInfoRec
     APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_##partition \
     }
 
-// static table correspond to enum NvRmModuleID in \include\nvrm_module.idl    
-// Expand this table to add more moduleID - partition map entries. 
+// static table correspond to enum NvRmModuleID in \include\nvrm_module.idl
+// Expand this table to add more moduleID - partition map entries.
 static const ObsInfo ObsInfoTable[] =
 {
   OBS_INFO_FIELD(Cpu, CPU),
@@ -86,16 +86,16 @@ McStatAp1x_Start(
         NvU32 client_id_1,
         NvU32 llc_client_id)
 {
-    NvU32 emc_ctrl = 
+    NvU32 emc_ctrl =
       (AREMC_STAT_CONTROL_MODE_BANDWIDTH << AREMC_STAT_CONTROL_MODE_SHIFT) |
       (AREMC_STAT_CONTROL_EVENT_QUALIFIED << AREMC_STAT_CONTROL_EVENT_SHIFT) |
-      (AREMC_STAT_CONTROL_CLIENT_TYPE_CMCR << 
+      (AREMC_STAT_CONTROL_CLIENT_TYPE_CMCR <<
          AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT) |  // default is CMC Read client
-      (AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE << 
+      (AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
          AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT) |
-      (AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE << 
+      (AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
          AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT);
-    
+
     NvU32 mc_filter_client_0 = (ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE <<
                    ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT);
 
@@ -117,40 +117,40 @@ McStatAp1x_Start(
     }
 
     if(llc_client_id == 1)
-        emc_ctrl |= AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER << 
-                    AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT; 
+        emc_ctrl |= AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER <<
+                    AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT;
                     // overwrite with MPCore read
-        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
-                0, EMC_STAT_CONTROL_0, 
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
                 NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER,DISABLE));
-        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
                 0, EMC_STAT_LLMC_CLOCK_LIMIT_0, 0xffffffff);
-        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
                 0, EMC_STAT_LLMC_CONTROL_0_0, emc_ctrl);
-        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController, 
-                0, EMC_STAT_CONTROL_0, 
+        NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
+                0, EMC_STAT_CONTROL_0,
                 NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, CLEAR));
         NV_REGW(rm, NvRmPrivModuleID_ExternalMemoryController,
-                0, EMC_STAT_CONTROL_0, 
+                0, EMC_STAT_CONTROL_0,
                 NV_DRF_DEF(EMC, STAT_CONTROL, LLMC_GATHER, ENABLE));
         NV_REGW(rm, NvRmPrivModuleID_MemoryController,
-                0, MC_STAT_CONTROL_0, 
+                0, MC_STAT_CONTROL_0,
                 NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, DISABLE));
         NV_REGW(rm, NvRmPrivModuleID_MemoryController,
                 0, MC_STAT_EMC_CLOCK_LIMIT_0, 0xffffffff);
         NV_REGW(rm, NvRmPrivModuleID_MemoryController,
                 0, MC_STAT_EMC_CONTROL_0_0,
-                (ARMC_STAT_CONTROL_MODE_BANDWIDTH << 
+                (ARMC_STAT_CONTROL_MODE_BANDWIDTH <<
                    ARMC_STAT_CONTROL_MODE_SHIFT) |
                 (client_id_0 << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT) |
-                (ARMC_STAT_CONTROL_EVENT_QUALIFIED << 
+                (ARMC_STAT_CONTROL_EVENT_QUALIFIED <<
                    ARMC_STAT_CONTROL_EVENT_SHIFT) |
                 mc_filter_client_0 |
-                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE << 
+                (ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE <<
                    ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT) |
                 (ARMC_STAT_CONTROL_FILTER_PRI_DISABLE <<
                    ARMC_STAT_CONTROL_FILTER_PRI_SHIFT) |
-                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE << 
+                (ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE <<
                    ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
         NV_REGW(rm, NvRmPrivModuleID_MemoryController,
                 0, MC_STAT_EMC_CONTROL_1_0,
@@ -168,9 +168,9 @@ McStatAp1x_Start(
                    ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT));
 
         NV_REGW(rm, NvRmPrivModuleID_MemoryController,
-                0, MC_STAT_CONTROL_0, 
+                0, MC_STAT_CONTROL_0,
                 NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, CLEAR));
-        NV_REGW(rm, NvRmPrivModuleID_MemoryController, 
+        NV_REGW(rm, NvRmPrivModuleID_MemoryController,
                 0, MC_STAT_CONTROL_0,
                 NV_DRF_DEF(MC, STAT_CONTROL, EMC_GATHER, ENABLE));
 }
@@ -206,15 +206,15 @@ McStatAp1x_Stop(
         NvU32 *llc_client_clocks,
         NvU32 *mc_clocks)
 {
-    *llc_client_cycles = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController, 
+    *llc_client_cycles = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
                            0, EMC_STAT_LLMC_COUNT_0_0);
-    *llc_client_clocks = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController, 
+    *llc_client_clocks = NV_REGR(rm, NvRmPrivModuleID_ExternalMemoryController,
                            0, EMC_STAT_LLMC_CLOCKS_0);
-    *client_0_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController, 
+    *client_0_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
                          0, MC_STAT_EMC_COUNT_0_0);
     *client_1_cycles = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
                          0, MC_STAT_EMC_COUNT_1_0);
-    *mc_clocks = NV_REGR(rm, NvRmPrivModuleID_MemoryController, 
+    *mc_clocks = NV_REGR(rm, NvRmPrivModuleID_MemoryController,
                    0, MC_STAT_EMC_CLOCKS_0);
 }
 
@@ -254,7 +254,7 @@ McStat_Report(
         NvU32 llc_client_cycles,
         NvU32 mc_clocks)
 {
-    NvOsDebugPrintf("LLC Client %d Count:  0x%.8X, %u\n", 
+    NvOsDebugPrintf("LLC Client %d Count:  0x%.8X, %u\n",
       llc_client_id, llc_client_cycles, llc_client_cycles);
     NvOsDebugPrintf("LLC Client %d Clocks: 0x%.8X, %u\n",
       llc_client_id, llc_client_clocks, llc_client_clocks);
@@ -266,7 +266,7 @@ McStat_Report(
 }
 
 //API to read data from OBS bus
-// The OBS_PART_SEL is mapped to the specified modID by obsInfoTable which is public in this file. 
+// The OBS_PART_SEL is mapped to the specified modID by obsInfoTable which is public in this file.
 
 NvError
 ReadObsData(
@@ -290,16 +290,16 @@ ReadObsData(
         }
     }
     if (i == ObsInfoTableSize)
-    {  
+    {
         return NvError_BadParameter;
     }
 
     for(offset = 0; offset < length; offset++)
     {
         index = start_index + offset;
-        temp = NV_DRF_DEF(APB_MISC_GP, OBSCTRL, OBS_EN, ENABLE) | 
-            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_MOD_SEL, modID) | 
-            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_PART_SEL, partID) | 
+        temp = NV_DRF_DEF(APB_MISC_GP, OBSCTRL, OBS_EN, ENABLE) |
+            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_MOD_SEL, modID) |
+            NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_PART_SEL, partID) |
             NV_DRF_NUM(APB_MISC_GP, OBSCTRL, OBS_SIG_SEL, index) ;
         NV_REGW(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0, temp);
         value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSCTRL_0);
@@ -309,7 +309,7 @@ ReadObsData(
             value1 = NV_REGR(rm, NvRmModuleID_Misc, 0, APB_MISC_GP_OBSDATA_0);
             timeout --;
         } while (value1 != value2 && timeout);
-        NvOsDebugPrintf("OBS bus modID 0x%x index 0x%x = value 0x%x", 
+        NvOsDebugPrintf("OBS bus modID 0x%x index 0x%x = value 0x%x",
                 modID, index, value1);
         value[offset] = value1;
     }
@@ -491,39 +491,39 @@ static void McErrorIntHandler(void* args)
     NvU32 IntStatus;
     NvU32 IntClear = 0;
     NvRmDeviceHandle hRm = (NvRmDeviceHandle)args;
-    
+
     IntStatus = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0);
     if ( NV_DRF_VAL(MC, INTSTATUS, DECERR_AXI_INT, IntStatus) )
     {
         IntClear |= NV_DRF_DEF(MC, INTSTATUS, DECERR_AXI_INT, SET);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_DECERR_AXI_ADR_0);
         NvOsDebugPrintf("AXI DecErrAddress=0x%x ", RegVal);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_DECERR_AXI_STATUS_0);
         NvOsDebugPrintf("AXI DecErrStatus=0x%x ", RegVal);
     }
     if ( NV_DRF_VAL(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, IntStatus) )
     {
         IntClear |= NV_DRF_DEF(MC, INTSTATUS, DECERR_EMEM_OTHERS_INT, SET);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_DECERR_EMEM_OTHERS_ADR_0);
         NvOsDebugPrintf("EMEM DecErrAddress=0x%x ", RegVal);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_DECERR_EMEM_OTHERS_STATUS_0);
         NvOsDebugPrintf("EMEM DecErrStatus=0x%x ", RegVal);
     }
     if ( NV_DRF_VAL(MC, INTSTATUS, INVALID_GART_PAGE_INT, IntStatus) )
     {
         IntClear |= NV_DRF_DEF(MC, INTSTATUS, INVALID_GART_PAGE_INT, SET);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_GART_ERROR_ADDR_0);
         NvOsDebugPrintf("GART DecErrAddress=0x%x ", RegVal);
-        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+        RegVal = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
                      MC_GART_ERROR_REQ_0);
         NvOsDebugPrintf("GART DecErrStatus=0x%x ", RegVal);
     }
-    
+
     NV_ASSERT(!"MC Decode Error ");
     // Clear the interrupt.
     NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_INTSTATUS_0, IntClear);
@@ -536,14 +536,14 @@ NvError NvRmPrivAp15McErrorMonitorStart(NvRmDeviceHandle hRm)
     NvU32 IrqList;
     NvError e = NvSuccess;
     NvOsInterruptHandler handler;
-    
+
     if (s_McInterruptHandle == NULL)
     {
         // Install an interrupt handler.
         handler = McErrorIntHandler;
         IrqList = NvRmGetIrqForLogicalInterrupt(hRm,
                       NvRmPrivModuleID_MemoryController, 0);
-        NV_CHECK_ERROR( NvRmInterruptRegister(hRm, 1, &IrqList,  &handler, 
+        NV_CHECK_ERROR( NvRmInterruptRegister(hRm, 1, &IrqList,  &handler,
             hRm, &s_McInterruptHandle, NV_TRUE) );
         // Enable Dec Err interrupts in memory Controller.
         val = NV_DRF_DEF(MC, INTMASK, DECERR_AXI_INTMASK, UNMASKED) |
@@ -567,7 +567,7 @@ void NvRmPrivAp15McErrorMonitorStop(NvRmDeviceHandle hRm)
 void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm)
 {
     NvU32   reg, mask;
-    reg = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0, 
+    reg = NV_REGR(hRm, NvRmPrivModuleID_MemoryController, 0,
               MC_LOWLATENCY_CONFIG_0);
     mask = NV_DRF_DEF(MC, LOWLATENCY_CONFIG, CMCR_LL_CTRL, ENABLE) |
            NV_DRF_DEF(MC, LOWLATENCY_CONFIG, CMCR_LL_SEND_BOTH, ENABLE) |
@@ -597,15 +597,13 @@ void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm)
 
     /* 2) Command Queue values should be 2,2,6 for better performance. */
     NV_REGW(hRm, NvRmPrivModuleID_ExternalMemoryController, 0, EMC_CMDQ_0,   0x00002206);
-    
+
     /* 3) MC_EMEM_ARB_CFG0_0 Should have optimal values for 166Mhz DRAM.
      *    27:22 EMEM_BANKCNT_NSP_TH (0xC seems to be better for 166Mhz)
      *    21:16 EMEM_BANKCNT_TH     (0x8 seems to be better for 166Mhz)
      *
-     *    MC_EMEM_ARB_CFG0_0 <= 0x0308_1010 
+     *    MC_EMEM_ARB_CFG0_0 <= 0x0308_1010
      */
-    
+
     NV_REGW(hRm, NvRmPrivModuleID_MemoryController, 0, MC_EMEM_ARB_CFG0_0,    0x03081010);
 }
-
-/******************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
index d9fd9f3d1251..6e33879da19f 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -485,7 +485,7 @@ void NvRmPrivIoPowerDetectStart(
     if ((hRmDeviceHandle->ChipId.Id == 0x15) ||
         (hRmDeviceHandle->ChipId.Id == 0x16))
     {
-        // On AP15/AP16 set/clear reset bit in PMC scratch0 
+        // On AP15/AP16 set/clear reset bit in PMC scratch0
         NvRmPrivAp15IoPowerDetectReset(hRmDeviceHandle);
 
         // For AP15 A01 chip the above reset does nothing, therefore
@@ -658,6 +658,3 @@ void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice)
     if (NvOdmPeripheralGetGuid(NV_VDD_DDR_RX_ODM_ID))
         NvRmPrivPmuRailControl(hRmDevice, NV_VDD_DDR_RX_ODM_ID, NV_TRUE);
 }
-
-/*****************************************************************************/
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c
index 40e8837f9e11..c964604c820c 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_clocks.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -216,7 +216,7 @@ NvRmPrivModuleClockAttach(
     }
 
     NV_ASSERT(cinfo->ClkEnableOffset);
-    reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+    reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
                   cinfo->ClkEnableOffset);
     Enabled = ((reg & cinfo->ClkEnableField) == cinfo->ClkEnableField);
     if (Enabled == Enable)
@@ -383,7 +383,7 @@ NvRmPrivMemoryClockReAttach(
 }
 
 void
-NvRmPrivExternalClockAttach( 
+NvRmPrivExternalClockAttach(
     NvRmDeviceHandle hDevice,
     NvRmClockSource SourceId,
     NvBool Enable)
@@ -430,7 +430,7 @@ NvRmPrivExternalClockAttach(
 
 /*****************************************************************************/
 
-void 
+void
 NvRmPrivEnableModuleClock(
     NvRmDeviceHandle hRmDevice,
     NvRmModuleID ModuleId,
@@ -440,10 +440,10 @@ NvRmPrivEnableModuleClock(
     {
         case 0x15:
         case 0x16:
-            Ap15EnableModuleClock(hRmDevice, ModuleId, ClockState); 
+            Ap15EnableModuleClock(hRmDevice, ModuleId, ClockState);
             break;
         case 0x20:
-            Ap20EnableModuleClock(hRmDevice, ModuleId, ClockState); 
+            Ap20EnableModuleClock(hRmDevice, ModuleId, ClockState);
             break;
         default:
             NV_ASSERT(!"Unsupported chip ID");
@@ -924,7 +924,7 @@ static void ModuleClockStateInit(NvRmDeviceHandle hRmDevice)
         {
             const NvRmCoreClockInfo* pCore =
                 NvRmPrivGetClockSourceHandle(cinfo->Sources[0])->pInfo.pCore;
-            NvRmClockSource SourceId = 
+            NvRmClockSource SourceId =
                 NvRmPrivCoreClockSourceGet(hRmDevice, pCore);
             NvRmPrivCoreClockReAttach(hRmDevice, pCore->SourceId, SourceId);
         }
@@ -976,7 +976,7 @@ NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice)
     {
         s_moduleClockTable = g_Ap15ModuleClockTable;
         s_moduleClockTableSize = g_Ap15ModuleClockTableSize;
-        NvRmPrivAp15PllReferenceTableInit(&s_PllReferencesTable, 
+        NvRmPrivAp15PllReferenceTableInit(&s_PllReferencesTable,
                 &s_PllReferencesTableSize);
         s_ClockSourceTable = NvRmPrivAp15ClockSourceTableInit();
         fpgaModuleFreq = FPGA_MODULE_KHZ_AP15;
@@ -985,7 +985,7 @@ NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice)
     {
         s_moduleClockTable = g_Ap20ModuleClockTable;
         s_moduleClockTableSize = g_Ap20ModuleClockTableSize;
-        NvRmPrivAp20PllReferenceTableInit(&s_PllReferencesTable, 
+        NvRmPrivAp20PllReferenceTableInit(&s_PllReferencesTable,
                 &s_PllReferencesTableSize);
         s_ClockSourceTable = NvRmPrivAp20ClockSourceTableInit();
         fpgaModuleFreq = FPGA_MODULE_KHZ_AP20;
@@ -1092,7 +1092,7 @@ NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice)
     if (env == ExecPlatform_Fpga)
     {
         for (i = 0; i < s_moduleClockTableSize; i++)
-        {                        
+        {
             s_moduleClockState[i].actual_freq = fpgaModuleFreq;
         }
     }
@@ -1346,7 +1346,7 @@ NvRmPrivGetInterfaceMaxClock(NvRmDeviceHandle hRmDevice, NvRmModuleID ModuleId)
 {
 
     NvU32 OdmModules[4];
-    NvU32 OdmInstances[4];        
+    NvU32 OdmInstances[4];
     NvU32* pMaxClockSpeed = NULL;
     NvU32 count = 0;
     NvU32 i = 0;
@@ -1364,12 +1364,12 @@ NvRmPrivGetInterfaceMaxClock(NvRmDeviceHandle hRmDevice, NvRmModuleID ModuleId)
         instance = OdmInstances[i];
         NvOdmQueryClockLimits(OdmModules[i], (const NvU32 **)&pMaxClockSpeed, &count);
         if ((pMaxClockSpeed) && (instance < count))
-        {       
+        {
             MaxFreq = pMaxClockSpeed[instance];
-        }            
+        }
     }
 
-    return MaxFreq;    
+    return MaxFreq;
 }
 
 NvRmFreqKHz
@@ -1543,7 +1543,7 @@ NvRmPowerModuleClockConfig (
     {
         if (env == ExecPlatform_Fpga || env == ExecPlatform_Qt)
         {
-            // Clock configuration only supported for the i2s, VI, i2c, 
+            // Clock configuration only supported for the i2s, VI, i2c,
             // dvc and HSMMC on this environment
             if (!(ModuleName == NvRmModuleID_I2s ||
                     ModuleName == NvRmModuleID_Vi ||
@@ -1640,7 +1640,7 @@ NvRmPowerModuleClockConfig (
             // for the i2s recording, the clock source to i2s should be less than
             // the system clock frequency 8.33MHz for the fpga, so dividing by 2
             // if its more than
-            if ((hDevice->ChipId.Id == 0x15 || hDevice->ChipId.Id == 0x16) && 
+            if ((hDevice->ChipId.Id == 0x15 || hDevice->ChipId.Id == 0x16) &&
                     (env == ExecPlatform_Fpga) && (ModuleName == NvRmModuleID_I2s))
             {
                 reg = NV_REGR(hDevice, NvRmPrivModuleID_ClockAndReset, 0,
@@ -1727,15 +1727,15 @@ NvRmPowerModuleClockConfig (
             hDevice, ModuleName, cinfo->ClkSourceOffset, flags);
 
 
-        /* 
+        /*
          * SDMMC internal feedback tap delay adjustment
          * This is required for the ap20 based boards.
-        */            
-        if ((PrefFreqListCount) && (hDevice->ChipId.Id == 0x20) && 
+        */
+        if ((PrefFreqListCount) && (hDevice->ChipId.Id == 0x20) &&
                 (ModuleName == NvRmModuleID_Sdio))
         {
             NvRmPrivAp20SdioTapDelayConfigure(hDevice, ModuleId,
-                    cinfo->ClkSourceOffset, state->actual_freq); 
+                    cinfo->ClkSourceOffset, state->actual_freq);
         }
     }
 
@@ -1838,15 +1838,15 @@ CoreClockSwitch(
     NvRmFreqKHz CoreFreq)
 {
     NvU32 reg;
-    
+
     // Construct core source control register settings.
     // Always use Idle clock mode; mode field = 2 ^ (Mode - 1)
     NV_ASSERT(pCinfo->SelectorOffset);
     NV_ASSERT(SourceIndex <= pCinfo->SourceFieldMasks[NvRmCoreClockMode_Idle]);
-        
+
     reg = ( ((0x1 << (NvRmCoreClockMode_Idle - 1)) << pCinfo->ModeFieldShift) |
-            (SourceIndex << pCinfo->SourceFieldShifts[NvRmCoreClockMode_Idle]) );    
-    
+            (SourceIndex << pCinfo->SourceFieldShifts[NvRmCoreClockMode_Idle]) );
+
     if (reg != NV_REGR(
         hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, pCinfo->SelectorOffset))
     {
@@ -1856,14 +1856,14 @@ CoreClockSwitch(
     }
 
     // Switch source and divider according to specified order. This guarantees
-    // that core frequency stays below maximum of "old" and "new" settings. 
+    // that core frequency stays below maximum of "old" and "new" settings.
     // Configure EMC LL path before and after clock switch.
     if (pCinfo->SourceId == NvRmClockSource_CpuBus)
         if ((hRmDevice->ChipId.Id == 0x15) || (hRmDevice->ChipId.Id == 0x16))
             NvRmPrivAp15SetEmcForCpuSrcSwitch(hRmDevice);
     if (SrcFirst)
     {
-        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0, 
+        NV_REGW(hRmDevice, NvRmPrivModuleID_ClockAndReset, 0,
                 pCinfo->SelectorOffset, reg);
         NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY);
     }
@@ -2055,13 +2055,13 @@ NvRmPrivCoreClockSet(
     NvRmFreqKHz CoreFreq = 0;
     NvU32 SrcIndex = NvRmClockSource_Num; // source index out of valid range
     ExecPlatform env;
-    
+
 
     NV_ASSERT(hRmDevice);
     NV_ASSERT(pCinfo);
-    
+
     env = NvRmPrivGetExecPlatform(hRmDevice);
-    
+
     if (env == ExecPlatform_Fpga)
         return;
 
@@ -2167,7 +2167,7 @@ GetSystemBusComplexHandle(NvRmDeviceHandle hRmDevice)
             s_SystemBusComplex.VclkDividendFieldSize = i;
         }
     }
-    return &s_SystemBusComplex; 
+    return &s_SystemBusComplex;
 }
 
 void
@@ -2270,7 +2270,7 @@ NvRmPrivBusClockFreqSet(
             *pVclkFreq = 0;
         s_ClockSourceFreq[NvRmClockSource_Vbus] = 0;
     }
-    
+
     /*
      * Set bus clocks dividers in bus rate control register.
      * Always enable all bus clocks.
@@ -2339,7 +2339,7 @@ NvRmPrivBusClockFreqGet(
     if (pCinfo->VclkDividendFieldMask)
     {
         NV_ASSERT(pVclkFreq);
-        *pVclkFreq = 
+        *pVclkFreq =
         (SystemFreq * (VclkDividend + 1)) >> pCinfo->VclkDividendFieldSize;
     }
     else if (pVclkFreq)
@@ -2742,7 +2742,7 @@ void NvRmPrivUnlockModuleClockState(void)
 
 // PLLC may be selected as a source only for Display, TVO, GPU, and VDE
 // modules. (It is also used for CPU and System/Avp core clocks, controlled
-// by DFS with its own configuration path - no need to specify here) 
+// by DFS with its own configuration path - no need to specify here)
 static const NvRmModuleID s_Ap15PllC0UsagePolicy[] =
 {
     NvRmModuleID_Display,
@@ -2766,7 +2766,7 @@ static const NvRmModuleID s_Ap20PllC0UsagePolicy[] =
 
 // PLLM may be selected as a source for GPU, UART and VDE modules. (It is also
 // used for EMC, CPU and System/Avp core clocks, controlled by DFS with its
-// own configuration path - no need to specify here) 
+// own configuration path - no need to specify here)
 static const NvRmModuleID s_Ap15PllM0UsagePolicy[] =
 {
     NvRmModuleID_GraphicsHost,
@@ -2925,7 +2925,7 @@ static void BackupClockSource(
     NvU32 reg, SourceIndex;
     NvRmModuleID ModuleId;
 
-    NV_ASSERT(pCinfo); 
+    NV_ASSERT(pCinfo);
     ModuleId = NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance);
 
     // Check if currently clock is disabled
@@ -2971,7 +2971,7 @@ static void RestoreClockSource(
     NvBool Disabled;
     NvRmModuleID ModuleId;
 
-    NV_ASSERT(pCinfo && pCstate); 
+    NV_ASSERT(pCinfo && pCstate);
     ModuleId = NVRM_MODULE_ID(pCinfo->Module, pCinfo->Instance);
 
     // Check if currently clock is disabled
@@ -3144,7 +3144,7 @@ PllCRestoreCpuClock(
     NvRmFreqKHz OldCpuFreq)
 {
     // Restore CPU clock as high as new PLLC0 output allows, provoded PLLC0
-    // was used as a source for CPU 
+    // was used as a source for CPU
     if (OldCpuFreq != 0)
     {
         NvRmClockSource SourceId = NvRmClockSource_PllC0;
@@ -3202,7 +3202,7 @@ PllCRestoreSystemClock(
     NvRmPrivDividerSet(hRmDevice, pSrcCinfo->pInfo.pDivider, divc1);
 
     // Restore System clock as high as new PLLC1 output allows, provoded PLLC1
-    // was used as a source for System clock 
+    // was used as a source for System clock
     if (OldSysFreq != 0)
     {
         SysFreq = NV_MIN(SysFreq, OldSysFreq);
@@ -3224,12 +3224,12 @@ NvRmFreqKHz NvRmPrivGetMaxFreqPllC(NvRmDeviceHandle hRmDevice)
 }
 
 /*
- * PLLC is reconfigured:  
+ * PLLC is reconfigured:
  * (a) when RM is setting fast clocks during boot/resume from deep sleep,
  *     provided PLLC is not already in use by any of the display heads
  * (b) when DDK/ODM is reconfiguring display clock (typically PLLC is required
  *     for CRT)
- * 
+ *
  * In both cases core voltage is set at nominal - reconfiguration is DVS-save.
  * Core clocks that use PLLC: CPU and System bus (starting with AP20) - are
  * switched to PLLP during reconfiguration and restored afterwards. Module
@@ -3304,8 +3304,3 @@ void NvRmPrivBoostPllC(NvRmDeviceHandle hRmDevice)
         )
         NvRmPrivReConfigurePllC(hRmDevice, NvRmFreqMaximum);
 }
-
-/*****************************************************************************/
-
-
-
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c
index f8b1b7322232..adb132093077 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/nvrm_diag.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -63,7 +63,7 @@ typedef struct DiagModuleMappingRec
     // respective module clock information structure
     NvU32 BaseIndex;
 
-    // Total number of the module instances 
+    // Total number of the module instances
     NvU32 InstancesNum;
 } DiagModuleMapping;
 
@@ -94,7 +94,7 @@ typedef struct NvRmDiagSourcesRec
     NvU32 ClockSourcesNum;
 
     // Map between clock source IDs and handles
-    NvRmDiagClockSourceHandle hSources[NvRmClockSource_Num]; 
+    NvRmDiagClockSourceHandle hSources[NvRmClockSource_Num];
 } NvRmDiagSources;
 
 // RM handle for diagnostic mode
@@ -106,7 +106,7 @@ NvRmDeviceHandle s_hDiagRm = NULL;
  */
 typedef struct NvRmDiagPowerRailRec
 {
-    // Power rail GUID 
+    // Power rail GUID
     NvU64 PowerRailId;
 
     // List of power group IDs mapped to this rail, terminated
@@ -149,7 +149,7 @@ static const NvRmDiagPowerRail s_Ap15PowerRailsTable[] =
             NV_POWERGROUP_NPG,
             NV_POWERGROUP_CPU,
             NV_POWERGROUP_TD,
-            NV_POWERGROUP_VE, 
+            NV_POWERGROUP_VE,
             NV_POWERGROUP_INVALID
         }
     },
@@ -305,7 +305,7 @@ static const NvRmDiagPowerRail s_Ap20PowerRailsTable[] =
         {
             NV_POWERGROUP_NPG,
             NV_POWERGROUP_TD,
-            NV_POWERGROUP_VE, 
+            NV_POWERGROUP_VE,
             NV_POWERGROUP_INVALID
         }
     },
@@ -550,7 +550,7 @@ NvRmDiagEnable(NvRmDeviceHandle hRmDevice)
     {
         NvRmDiagModuleID id = s_Modules.ModuleClockTable[i].DiagModuleID;
         NV_ASSERT((0 < id) && (id < NvRmDiagModuleID_Num));
-        s_Modules.InstancesMap[id].InstancesNum++; 
+        s_Modules.InstancesMap[id].InstancesNum++;
     }
 
     // 2nd pass - fill in mapping indexes
@@ -650,7 +650,7 @@ NvRmDiagListClockSources(
     NvRmDiagClockSourceHandle* phSourceList)
 {
     NvU32 SourcesNum, i;
-    NV_ASSERT(pListSize);    
+    NV_ASSERT(pListSize);
     NV_ASSERT(phSourceList);
 
     if (s_hDiagRm == NULL)
@@ -694,7 +694,7 @@ NvRmDiagModuleListClockSources(
     NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
     NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
 
-    NV_ASSERT(pListSize);    
+    NV_ASSERT(pListSize);
     NV_ASSERT(phSourceList);
 
     if (s_hDiagRm == NULL)
@@ -783,7 +783,7 @@ NvRmDiagModuleClockConfigure(
     {
         return NvError_NotInitialized;
     }
-    
+
     // Verify source handle, module id, and get module info
     NV_ASSERT((hSource != NULL) &&
         (Module < NvRmDiagModuleID_Num) &&
@@ -804,7 +804,7 @@ NvRmDiagModuleClockConfigure(
     NV_ASSERT(SrcIndex != NvRmClockSource_Num);
     if ((pCinfo->SourceFieldMask == 0) && (pCinfo->DivisorFieldMask == 0))
     {
-        return NvSuccess; 
+        return NvSuccess;
     }
     NV_ASSERT(SrcIndex <= pCinfo->SourceFieldMask);
 
@@ -967,7 +967,7 @@ NvRmDiagClockSourceGetScaler(NvRmDiagClockSourceHandle hSource)
 }
 
 NvError
-NvRmDiagClockSourceListSources( 
+NvRmDiagClockSourceListSources(
     NvRmDiagClockSourceHandle hSource,
     NvU32* pListSize,
     NvRmDiagClockSourceHandle * phSourceList)
@@ -975,7 +975,7 @@ NvRmDiagClockSourceListSources(
     NvRmClockSource source = NvRmClockSource_Invalid;
     NvRmClockSource* Sources = NULL;
 
-    NV_ASSERT(pListSize);    
+    NV_ASSERT(pListSize);
     NV_ASSERT(phSourceList);
 
     if (s_hDiagRm == NULL)
@@ -1016,7 +1016,7 @@ NvRmDiagClockSourceListSources(
     {
         // Return total number of input sources if no room for the output list,
         // otherwise return sources list (min of requested and total size)
-        NvU32 SourcesNum, i; 
+        NvU32 SourcesNum, i;
         for (SourcesNum = 0, i = 0; i < NvRmClockSource_Num; i++)
         {
             NvRmClockSource source = Sources[i];
@@ -1068,7 +1068,7 @@ NvU32 NvRmDiagOscillatorGetFreq(NvRmDiagClockSourceHandle hOscillator)
 }
 
 NvError
-NvRmDiagPllConfigure( 
+NvRmDiagPllConfigure(
     NvRmDiagClockSourceHandle hPll,
     NvU32 M,
     NvU32 N,
@@ -1088,7 +1088,7 @@ NvRmDiagPllConfigure(
 }
 
 NvError
-NvRmDiagClockScalerConfigure( 
+NvRmDiagClockScalerConfigure(
     NvRmDiagClockSourceHandle hScaler,
     NvRmDiagClockSourceHandle hInput,
     NvU32 M,
@@ -1236,7 +1236,7 @@ NvRmDiagModuleListPowerRails(
     NvU32 Instance = NVRM_DIAG_MODULE_INSTANCE(id);
     NvRmDiagModuleID Module = NVRM_DIAG_MODULE_ID(id);
 
-    NV_ASSERT(pListSize);    
+    NV_ASSERT(pListSize);
     NV_ASSERT(phRailList);
 
     if (s_hDiagRm == NULL)
@@ -1358,7 +1358,7 @@ NvBool NvRmPrivIsDiagMode(NvRmModuleID ModuleId)
 
     if (ModuleId == NvRmModuleID_Invalid)
         return NV_TRUE;     // Report diagnostic is in progress
-    
+
     // Report diagnostic is in progress for any module except PMU bus host
     return (ModuleId != s_Rails.PmuBusHostRmId);
 }
@@ -1371,6 +1371,3 @@ NvBool NvRmDiagIsLockSupported(void)
     return NV_FALSE;
 #endif
 }
-
-/*****************************************************************************/
-
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c
index 8935101c4929..e1fac2bc6d66 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_clocks_limits.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -204,7 +204,7 @@ NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice)
     }
 
     // Set AVP upper clock boundary with combined Absolute/Scaled limit;
-    // Sync System clock with AVP (System is not in relocation table) 
+    // Sync System clock with AVP (System is not in relocation table)
     s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz = AvpMaxKHz;
     s_ClockRangeLimits[NvRmPrivModuleID_System].MaxKHz =
         s_ClockRangeLimits[NvRmModuleID_Avp].MaxKHz;
@@ -239,7 +239,7 @@ NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice)
     }
     else if (hRmDevice->ChipId.Id == 0x20)
     {
-        // No CMC; TODO: Mselect/CPU <= 1/4? 
+        // No CMC; TODO: Mselect/CPU <= 1/4?
         s_ClockRangeLimits[NvRmPrivModuleID_Mselect].MaxKHz = CpuMaxKHz >> 2;
     }
     else
@@ -497,7 +497,7 @@ NvRmPrivModuleVscaleAttach(
         s_VoltageStepRefCounts[vstep1]--;
         if ((pCinfo->Module == NvRmModuleID_Usb2Otg) &&
             (hRmDevice->ChipId.Id == 0x16))
-        {   
+        {
             // Two AP16 USB modules share clock enable control
             NV_ASSERT(s_VoltageStepRefCounts[vstep1]);
             s_VoltageStepRefCounts[vstep1]--;
@@ -564,7 +564,7 @@ NvRmPrivModuleVscaleReAttach(
     }
 
     // Find voltage step for using the target source, and select maximum
-    // step required for both module and its source to operate 
+    // step required for both module and its source to operate
     pScale = s_pClockScales[NvRmClkLimitsExtID_ClkSrc];
     NV_ASSERT(pScale);
     for (j = 0; j < s_ChipFlavor.pSocShmoo->ShmooVmaxIndex; j++)
@@ -771,7 +771,7 @@ static NvError NvRmBootArgChipShmooGet(
     {
         err = NvRmMemHandleClaimPreservedHandle(
             hRmDevice, BootArgSh.MemHandleKey, &hMem);
-        if (err != NvSuccess) 
+        if (err != NvSuccess)
         {
             goto fail;
         }
@@ -821,7 +821,7 @@ static NvError NvRmBootArgChipShmooGet(
             err = NvError_InsufficientMemory;
             goto fail;
         }
-        
+
         // Map the physical shmoo address passed by the backdoor loader
         err = NvOsPhysicalMemMap(BootArgShPhys.PhysShmooPtr, TotalSize,
             NvOsMemAttribute_WriteBack, 0, &pBootShmooData);
@@ -848,7 +848,7 @@ static NvError NvRmBootArgChipShmooGet(
     size = BootArgSh.CoreShmooVoltagesListSize;
     NV_ASSERT (offset + size <= TotalSize);
     s_SocShmoo.ShmooVoltages = (const NvU32*)((NvUPtr)s_pShmooData + offset);
-    size /= sizeof(*s_SocShmoo.ShmooVoltages); 
+    size /= sizeof(*s_SocShmoo.ShmooVoltages);
     NV_ASSERT((size * sizeof(*s_SocShmoo.ShmooVoltages) ==
               BootArgSh.CoreShmooVoltagesListSize) && (size > 1));
     s_SocShmoo.ShmooVmaxIndex = size - 1;
@@ -934,7 +934,7 @@ NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
 #define NVRM_BOOT_MEM_ALIGNMENT (0x1 << 12)
 #define NVRM_BOOT_MEM_SIZE (0x1 << 13)
 
-    static const NvRmHeap s_heaps[] = 
+    static const NvRmHeap s_heaps[] =
     {
         NvRmHeap_ExternalCarveOut,
     };
@@ -951,13 +951,13 @@ NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
     // Pack shmoo arrays and structures (all members are of NvU32 type).
     // Start with core domain.
     BootArgSh.CoreShmooVoltagesListOffset = size;
-    BootArgSh.CoreShmooVoltagesListSize = 
+    BootArgSh.CoreShmooVoltagesListSize =
         (pChipFlavor->pSocShmoo->ShmooVmaxIndex + 1) *
         sizeof(*pChipFlavor->pSocShmoo->ShmooVoltages);
     size += BootArgSh.CoreShmooVoltagesListSize;
 
     BootArgSh.CoreScaledLimitsListOffset = size;
-    BootArgSh.CoreScaledLimitsListSize = 
+    BootArgSh.CoreScaledLimitsListSize =
         pChipFlavor->pSocShmoo->ScaledLimitsListSize *
         sizeof(*pChipFlavor->pSocShmoo->ScaledLimitsList);
     size += BootArgSh.CoreScaledLimitsListSize;
@@ -969,7 +969,7 @@ NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
     size += BootArgSh.OscDoublerListSize;
 
     BootArgSh.SKUedLimitsOffset = size;
-    BootArgSh.SKUedLimitsSize = 
+    BootArgSh.SKUedLimitsSize =
         sizeof(*pChipFlavor->pSocShmoo->pSKUedLimits);
     size += BootArgSh.SKUedLimitsSize;
 
@@ -977,13 +977,13 @@ NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
     {
         // Add data for dedicated CPU domain
         BootArgSh.CpuShmooVoltagesListOffset = size;
-        BootArgSh.CpuShmooVoltagesListSize = 
+        BootArgSh.CpuShmooVoltagesListSize =
             (pChipFlavor->pCpuShmoo->ShmooVmaxIndex + 1) *
             sizeof(*pChipFlavor->pCpuShmoo->ShmooVoltages);
         size += BootArgSh.CpuShmooVoltagesListSize;
 
         BootArgSh.CpuScaledLimitsOffset = size;
-        BootArgSh.CpuScaledLimitsSize = 
+        BootArgSh.CpuScaledLimitsSize =
             sizeof(*pChipFlavor->pCpuShmoo->pScaledCpuLimits);
         size += BootArgSh.CpuScaledLimitsSize;
     }
@@ -1031,10 +1031,10 @@ NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice)
     if (pChipFlavor->pCpuShmoo)
     {
         NvRmMemWrite(hMem, BootArgSh.CpuShmooVoltagesListOffset,
-            pChipFlavor->pCpuShmoo->ShmooVoltages, 
+            pChipFlavor->pCpuShmoo->ShmooVoltages,
             BootArgSh.CpuShmooVoltagesListSize);
         NvRmMemWrite(hMem, BootArgSh.CpuScaledLimitsOffset,
-            pChipFlavor->pCpuShmoo->pScaledCpuLimits, 
+            pChipFlavor->pCpuShmoo->pScaledCpuLimits,
             BootArgSh.CpuScaledLimitsSize);
     }
 
@@ -1065,6 +1065,3 @@ fail:
     return NvSuccess;
 #endif
 }
-
-/*****************************************************************************/
-
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c
index 151a5d5a61b6..fc3fa8c683a7 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_module.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -233,15 +233,14 @@ NvRmQueryChipUniqueId(NvRmDeviceHandle hDevHandle, NvU32 IdSize, void* pId)
         return NvError_BadParameter;
     }
 
+    NvOsMemset(pId, 0, Size);
     switch (hDevHandle->ChipId.Id)
     {
     case 0x15:
     case 0x16:      // ap16 should use same space of ap15 for fuse info.
-        NvOsMemset(pId, 0, Size);
         err = NvRmPrivAp15ChipUniqueId(hDevHandle,pId);
         break;
     case 0x20:
-        NvOsMemset(pId, 0, Size);
         err = NvRmPrivAp20ChipUniqueId(hDevHandle,pId);
         break;
     default:
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
index c35dec9f4022..92653bc6074f 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * Copyright (c) 2008-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -178,6 +178,7 @@ typedef struct
     (*pfnSetDefaultTristate)(
         NvRmDeviceHandle hDevice);
 } NvPinmuxPrivMethods;
+
     static NvPinmuxPrivMethods s_PinmuxMethods =
     {
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
@@ -411,13 +412,13 @@ NvU32 NvRmPrivRmModuleToOdmModule(
 
     NV_ASSERT(pOdmModules && pOdmInstances);
 
-    if (ChipId==0x20)
-    {
-        Result = NvRmPrivAp20RmModuleToOdmModule(RmModule,
-             pOdmModules, pOdmInstances, &Cnt);
-    } else {
-        return 0;
-    }
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
+    NV_ASSERT(ChipId==0x20);
+    Result = NvRmPrivAp20RmModuleToOdmModule(RmModule,
+         pOdmModules, pOdmInstances, &Cnt);
+#else
+#error "Unsupported Tegra architecture"
+#endif
 
     /*  A default mapping is provided for all standard I/O controllers,
      *  if the chip-specific implementation does not implement a mapping */
@@ -745,4 +746,3 @@ NvError NvRmGetStraps(
         return NvError_BadParameter;
     return (s_PinmuxMethods.pfnGetStraps)(hDevice, StrapGroup, pStrapValue);
 }
-
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
index 3a90c08a9070..5af5e00562e2 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_pinmux_utils.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * Copyright (c) 2008-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -322,5 +322,3 @@ void NvRmAp20SetDefaultTristate (NvRmDeviceHandle hDevice);
 #endif  /* __cplusplus */
 
 #endif // NVRM_PINMUX_UTILS_H
-
-
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
index 7ac8d331fecc..c8ca30d059cb 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,14 +30,14 @@
  *
  */
 
-/** 
+/**
  * @file
- * @brief <b>nVIDIA Driver Development Kit: 
+ * @brief <b>nVIDIA Driver Development Kit:
  *           Power Resource manager </b>
  *
  * @b Description: Implements NvRM Dynamic Voltage and Frequency Scaling for
  *                  for SOC-wide clock domains.
- * 
+ *
  */
 
 #include "nvrm_power_dfs.h"
@@ -164,9 +164,9 @@ static DfsProfile s_Profile = {{0}};
 
 #else
 
-#define DfsProfileInit(pDfs) 
-#define DfsProfileStart(pDfs, ProfileId) 
-#define DfsProfileSample(pDfs, ProfileId) 
+#define DfsProfileInit(pDfs)
+#define DfsProfileStart(pDfs, ProfileId)
+#define DfsProfileSample(pDfs, ProfileId)
 #endif
 
 /*****************************************************************************/
@@ -314,7 +314,7 @@ static NvError SystatMonitorsGetCapabilities(NvRmDfs* pDfs);
 static NvError VdeMonitorsGetCapabilities(NvRmDfs* pDfs);
 static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs);
 
-/*                         
+/*
  *  Gets monitoring capabilities of all DFS modules
  */
 static NvError DfsGetModulesCapabilities(NvRmDfs* pDfs);
@@ -396,7 +396,7 @@ AddActivitySample(
     NvU32 ActiveCount);
 
 // Determine PM thread request for CPU state control
-static NvRmPmRequest 
+static NvRmPmRequest
 DfsGetPmRequest(
     NvRmDeviceHandle hRmDevice,
     NvRmDfsSampler* pCpuSampler,
@@ -406,7 +406,7 @@ DfsGetPmRequest(
 
 /*
  * DFS clock control thread entry point and termination function
- */ 
+ */
 static NvRmPmRequest DfsThread(NvRmDfs* pDfs);
 static void DfsThreadTerminate(NvRmDfs* pDfs);
 
@@ -440,7 +440,7 @@ DfsClipCpuEmcHighLimits(
 
 /*
  * Emulate sampling results to achieve specified average frequency
- * provided it is bigger than the current one 
+ * provided it is bigger than the current one
  */
 static void
 DfsSetAverageUp(
@@ -466,7 +466,7 @@ DvsChangeCpuVoltage(
     NvRmDvs* pDvs,
     NvRmMilliVolts TargetMv);
 
-/* 
+/*
  * Enable/Disable voltage scaling
  */
 static void NvRmPrivDvsRun(void);
@@ -516,7 +516,7 @@ static NvError SystatMonitorsGetCapabilities(NvRmDfs* pDfs)
 
     /*
      * System Statistic module includes activity monitors for CPU, AVP, AHB,
-     * and APB domains. Its presence is required for DFS to work.   
+     * and APB domains. Its presence is required for DFS to work.
      */
     SystatCaps[0].DomainMap[NvRmDfsClockId_Cpu] = NV_TRUE;
     SystatCaps[0].DomainMap[NvRmDfsClockId_Avp] = NV_TRUE;
@@ -606,7 +606,7 @@ static NvError VdeMonitorsGetCapabilities(NvRmDfs* pDfs)
     }
     else
     {
-        // If get capabilities failed, set "not present" cpabilities 
+        // If get capabilities failed, set "not present" cpabilities
         pCaps = &VdeCaps[0];
     }
     pDfs->Modules[NvRmDfsModuleId_Vde] = *pCaps;
@@ -629,7 +629,7 @@ static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs)
 
     /*
      * EMC module includes activity monitor for EMC clock domain. This
-     * monitor may, or may not be present on different versions of EMC 
+     * monitor may, or may not be present on different versions of EMC
      */
     EmcCaps[0].DomainMap[NvRmDfsClockId_Emc] = NV_FALSE;
 
@@ -645,7 +645,7 @@ static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs)
     EmcCaps[2].Start = NvRmPrivAp20EmcMonitorsStart;
     EmcCaps[2].Read = NvRmPrivAp20EmcMonitorsRead;
 
-    ModuleCaps[0].MajorVersion = 1; // AP15 A01       
+    ModuleCaps[0].MajorVersion = 1; // AP15 A01
     ModuleCaps[0].MinorVersion = 0;
     ModuleCaps[0].EcoLevel = 0;
     ModuleCaps[0].Capability = (void*)&EmcCaps[1];
@@ -666,14 +666,14 @@ static NvError EmcMonitorsGetCapabilities(NvRmDfs* pDfs)
     if (error == NvSuccess)
     {
         if (pCaps->DomainMap[NvRmDfsClockId_Emc])
-        {       
+        {
             pCaps->pBaseReg = (tbl->ModInst +
                 tbl->Modules[NvRmPrivModuleID_ExternalMemoryController].Index)->VirtAddr;
         }
     }
     else
     {
-        // If get capabilities failed, set "not present" cpabilities 
+        // If get capabilities failed, set "not present" cpabilities
         pCaps = &EmcCaps[0];
     }
     pDfs->Modules[NvRmDfsModuleId_Emc] = *pCaps;
@@ -994,7 +994,7 @@ DfsReadMonitors(
     }
 }
 
-static NvRmPmRequest 
+static NvRmPmRequest
 DfsGetPmRequest(
     NvRmDeviceHandle hRmDevice,
     NvRmDfsSampler* pCpuSampler,
@@ -1025,7 +1025,7 @@ DfsGetTargetFrequencies(
     // Add current sample interval to sampling window; always signal to clock
     // control thread if window wraparound; check busy hints expirtaion time
     ReturnValue = AddSampleInterval(&pDfs->SamplingWindow, msec);
-    pDfs->SamplingWindow.SampleCnt++; 
+    pDfs->SamplingWindow.SampleCnt++;
     BusyCheckTime = pDfs->SamplingWindow.BusyCheckDelayUs <
         (usec - pDfs->SamplingWindow.BusyCheckLastUs);
 
@@ -1091,7 +1091,7 @@ DfsGetTargetFrequencies(
             ActiveCount =
                 (ActiveCount > IdleCount) ? (ActiveCount - IdleCount) : (0);
 #if NVRM_DFS_STALL_AVERAGE_IN_BUSY_PULSE
-            if (!pDomainSampler->BusyPulseMode) 
+            if (!pDomainSampler->BusyPulseMode)
 #endif
             {
                 AddActivitySample(pDomainSampler, ActiveCount);
@@ -1136,14 +1136,14 @@ DfsGetTargetFrequencies(
             }
 
             // Average frequency change is recognized by DFS only if it exceeds
-            // tolerance band. 
+            // tolerance band.
             if ((pDomainSampler->AverageKHz + pDomainParam->LowerBandKHz) <
                 pDomainSampler->BumpedAverageKHz)
             {
                 pDomainSampler->BumpedAverageKHz =
                     pDomainSampler->AverageKHz + pDomainParam->LowerBandKHz;
             }
-            else if (pDomainSampler->AverageKHz > 
+            else if (pDomainSampler->AverageKHz >
                 (pDomainSampler->BumpedAverageKHz + pDomainParam->UpperBandKHz))
             {
                 pDomainSampler->BumpedAverageKHz =
@@ -1230,7 +1230,7 @@ DfsGetTargetFrequencies(
                 LowCornerDomainKHz = NV_MAX(DomainBusyKHz, LowCornerDomainKHz);
         }
 
-        if ( ((*pDomainKHz) > 
+        if ( ((*pDomainKHz) >
               (LowCornerDomainKHz + pDomainParam->NrtStarveParam.BoostStepKHz))
              || (((*pDomainKHz) > LowCornerDomainKHz) && (!pDfs->LowCornerHit))
             )
@@ -1240,7 +1240,7 @@ DfsGetTargetFrequencies(
 
         /*
          * Update PM request. Set return value if CPU power state change
-         * is requested. 
+         * is requested.
          */
         if (i == NvRmDfsClockId_Cpu)
         {
@@ -1281,11 +1281,11 @@ AddSampleInterval(
 {
     /*
      * Add current sampling interval to the sampling window (i.e., replace the
-     * first/"oldest" interval with the new one and update window size). 
-     */ 
+     * first/"oldest" interval with the new one and update window size).
+     */
     NvBool WrapAround = NV_FALSE;
 
-    NvU32* pFirst = pSampleWindow->pLastInterval + 1; 
+    NvU32* pFirst = pSampleWindow->pLastInterval + 1;
     if (pFirst >= &pSampleWindow->IntervalsMs[
         NV_ARRAY_SIZE(pSampleWindow->IntervalsMs)])
     {
@@ -1308,8 +1308,8 @@ AddActivitySample(
 {
     /*
      * Add new activity sample to the cicular buffer(i.e., replace the
-     * first/"oldest" sample with the new one) and update total cycle count 
-     */ 
+     * first/"oldest" sample with the new one) and update total cycle count
+     */
     NvU32* pFirst = pDomainSampler->pLastSample + 1;
     if (pFirst >= &pDomainSampler->Cycles[
         NV_ARRAY_SIZE(pDomainSampler->Cycles)])
@@ -1355,7 +1355,7 @@ static void DfsIsr(void* args)
 
     if (pDfs->DfsRunState > NvRmDfsRunState_Stopped)
     {
-        // If DFS is running re-start monitors, execute DFS algorithm, and 
+        // If DFS is running re-start monitors, execute DFS algorithm, and
         // determine new target frequencies for the clock control thread
         DfsStartMonitors(pDfs, &DfsKHz, msec);
         ClockChange = DfsGetTargetFrequencies(&IdleData, pDfs, &DfsKHz);
@@ -1422,7 +1422,7 @@ static NvRmPmRequest DfsThread(NvRmDfs* pDfs)
         /*
          * On exit from low power state re-initialize DFS h/w, samplers, and
          * start monitors provided DFS is running. If DFS is stopped just get
-         * DFS h/w ready. 
+         * DFS h/w ready.
          */
         NV_ASSERT_SUCCESS(NvRmPowerGetEvent(
             pDfs->hRm, pDfs->PowerClientId, &PowerEvent));
@@ -1478,7 +1478,7 @@ static NvRmPmRequest DfsThread(NvRmDfs* pDfs)
         {
             NeedClockUpdate = NV_FALSE;
             BusyCheckDelayMs = NVRM_DFS_BUSY_PURGE_MS;
-            
+
             for (i = 1; i < NvRmDfsClockId_Num; i++)
             {
                 NvRmFreqKHz NewBusyKHz;
@@ -1548,7 +1548,7 @@ static NvRmPmRequest DfsThread(NvRmDfs* pDfs)
         }
         else
         {
-            // DFS is stopped - thread is signaled by API, always update clock 
+            // DFS is stopped - thread is signaled by API, always update clock
             NeedClockUpdate = NV_TRUE;
         }
 
@@ -1578,7 +1578,7 @@ static NvRmPmRequest DfsThread(NvRmDfs* pDfs)
             }
             NvRmPrivUnlockSharedPll();
 
-            // Complete synchronous busy hint processing. 
+            // Complete synchronous busy hint processing.
             if (pDfs->BusySyncState == NvRmDfsBusySyncState_Execute)
             {
                 pDfs->BusySyncState = NvRmDfsBusySyncState_Idle;
@@ -1650,7 +1650,7 @@ DfsClockFreqGet(
     NvRmDfsFrequencies* pDfsKHz)
 {
     NvU32 i;
- 
+
     switch (s_Platform)
     {
         case ExecPlatform_Soc:
@@ -1768,7 +1768,7 @@ DttClockUpdate(
 
     // Check if thermal throttling is supported
     if (NVRM_DTT_DISABLED || (!pDtt->hOdmTcore))
-        return NV_FALSE; 
+        return NV_FALSE;
 
     if (pDtt->TcorePolicy.UpdateFlag)
     {
@@ -1961,7 +1961,7 @@ NvError NvRmPrivDfsInit(NvRmDeviceHandle hRmDeviceHandle)
         goto failed;
     }
 
-    /* 
+    /*
      * Get DFS modules capbilities, check which activity monitors are
      * supported, and initialize monitor access function pointers. Then
      * initialize DFS samples and H/w monitors
@@ -1984,20 +1984,20 @@ NvError NvRmPrivDfsInit(NvRmDeviceHandle hRmDeviceHandle)
      * trigger DFS algorithm execution
      */
     {
-        pDfs->IrqNumber = NvRmGetIrqForLogicalInterrupt(hRmDeviceHandle, 
-                NVRM_MODULE_ID(NvRmModuleID_SysStatMonitor, 0), 
+        pDfs->IrqNumber = NvRmGetIrqForLogicalInterrupt(hRmDeviceHandle,
+                NVRM_MODULE_ID(NvRmModuleID_SysStatMonitor, 0),
                 0);
     }
     if (!pDfs->DfsInterruptHandle)
     {
         NvU32 IrqList = (NvU32)pDfs->IrqNumber;
         NvOsInterruptHandler hDfsIsr = DfsIsr;
-        error = NvRmInterruptRegister(hRmDeviceHandle, 1, 
+        error = NvRmInterruptRegister(hRmDeviceHandle, 1,
                 &IrqList, &hDfsIsr, pDfs, &pDfs->DfsInterruptHandle, NV_TRUE);
         if (error != NvSuccess)
         {
             // Set IRQ invalid to avoid deregistration of other module interrupt
-            pDfs->IrqNumber = NVRM_IRQ_INVALID;  
+            pDfs->IrqNumber = NVRM_IRQ_INVALID;
             goto failed;
         }
     }
@@ -2033,7 +2033,7 @@ void NvRmPrivDfsDeinit(NvRmDeviceHandle hRmDeviceHandle)
     NvOsMutexDestroy(pDfs->hSyncBusyMutex);
     NvRmPowerUnRegister(hRmDeviceHandle, pDfs->PowerClientId);
     NvOsSemaphoreDestroy(pDfs->hSemaphore);
-    NvOsIntrMutexDestroy(pDfs->hIntrMutex); 
+    NvOsIntrMutexDestroy(pDfs->hIntrMutex);
     NvOsMemset(pDfs, 0, sizeof(NvRmDfs));
 }
 
@@ -2117,13 +2117,13 @@ void NvRmPrivStarvationHintPrintf(
     {
         NvU32 i;
         char ClientName[sizeof(ClientTag)+ 1];
-        ClientTagToString(ClientTag, ClientName); 
+        ClientTagToString(ClientTag, ClientName);
 
         for (i = 0; i < NumHints; i++)
         {
             const NvRmDfsStarvationHint* pHint = &pMultiHint[i];
             NvOsDebugPrintf("%s starvation hint: %s from client %3d (%s)\n",
-                            s_DfsDomainNames[pHint->ClockId], 
+                            s_DfsDomainNames[pHint->ClockId],
                             (pHint->Starving ? "TRUE " : "FALSE"),
                             ClientId, ClientName);
         }
@@ -2164,7 +2164,7 @@ void NvRmPrivBusyHintPrintf(
     {
         NvU32 i;
         char ClientName[sizeof(ClientTag)+ 1];
-        ClientTagToString(ClientTag, ClientName); 
+        ClientTagToString(ClientTag, ClientName);
 
         for (i = 0; i < NumHints; i++)
         {
@@ -2422,7 +2422,7 @@ void NvRmPrivVoltageScale(
     NvRmDfs* pDfs = &s_Dfs;
     NvRmDvs* pDvs = &s_Dfs.VoltageScaler;
     NvBool DedicatedCpuRail = NvRmPrivIsCpuRailDedicated(pDfs->hRm);
-    
+
     /* Some systems(ex. FPGA) does have power rail control. */
     if (!pDvs->RtcRailAddress || !pDvs->CoreRailAddress)
         return;
@@ -2461,7 +2461,7 @@ void NvRmPrivVoltageScale(
 
         // Increase voltage before changing frequency, and vice versa;
         // Change core 1st before changing frequency, and vice versa
-        // (to guarantee required margin of core voltage over CPU voltage) 
+        // (to guarantee required margin of core voltage over CPU voltage)
         if (BeforeFreqChange)
         {
             if (pDvs->Lp2SyncOTPFlag)
@@ -2609,9 +2609,9 @@ void NvRmPrivDfsSuspend(NvOdmSocPowerState state)
                 pDfs->hRm, NVRM_AP20_SUSPEND_CORE_MV, &pDfs->SuspendKHz);
         else
             pDfs->SuspendKHz = pDfs->LowCornerKHz; // Low corner by default
-        pDfs->SuspendKHz.Domains[0] = NvRmFreqMaximum;   
+        pDfs->SuspendKHz.Domains[0] = NvRmFreqMaximum;
     }
-    
+
     NvRmPrivLockSharedPll();
     if (state == NvOdmSocPowerState_DeepSleep)
     {
@@ -2726,7 +2726,7 @@ void NvRmPrivDttInit(NvRmDeviceHandle hRmDeviceHandle)
         !pDtt->TcoreHighLimitCaps.OdmProtected)
     {
         // Sanity checks to make sure out-of-limit interrupt is available in
-        // the entire temperature range 
+        // the entire temperature range
         NV_ASSERT(pDtt->TcoreLowLimitCaps.MinValue <= pDtt->TcoreCaps.Tmin);
         NV_ASSERT(pDtt->TcoreHighLimitCaps.MinValue <= pDtt->TcoreCaps.Tmin);
         NV_ASSERT(pDtt->TcoreLowLimitCaps.MaxValue >= pDtt->TcoreCaps.Tmax);
@@ -2780,10 +2780,10 @@ NvRmDfsSetState(
     NvRmDfsFrequencies DfsKHz;
     NvError error = NvSuccess;
     NvRmDfs* pDfs = &s_Dfs;
-    
+
     NV_ASSERT(hRmDeviceHandle);
     NV_ASSERT(pDfs->hIntrMutex);
-    NV_ASSERT((0 < NewDfsRunState) && (NewDfsRunState < NvRmDfsRunState_Num)); 
+    NV_ASSERT((0 < NewDfsRunState) && (NewDfsRunState < NvRmDfsRunState_Num));
 
     NvRmPrivLockSharedPll();
     DfsClockFreqGet(hRmDeviceHandle, &DfsKHz);
@@ -2797,7 +2797,7 @@ NvRmDfsSetState(
 
     /*
      * State transition procedures
-     */ 
+     */
     switch (NewDfsRunState)
     {
         // On transition to running states from stopped state samplers are
@@ -2843,7 +2843,7 @@ NvRmDfsSetLowCorner(
 {
     NvU32 i;
     NvRmDfs* pDfs = &s_Dfs;
-    
+
     NV_ASSERT(hRmDeviceHandle);
     NV_ASSERT(pDfs->hIntrMutex);
     NV_ASSERT(DfsFreqListCount == NvRmDfsClockId_Num);
@@ -2935,7 +2935,7 @@ NvRmDfsSetAvHighCorner(
         DfsAvSystemHighKHz = pDfs->HighCornerKHz.Domains[NvRmDfsClockId_System];
     else if (DfsAvSystemHighKHz > pDfs->DfsParameters[NvRmDfsClockId_System].MaxKHz)
         DfsAvSystemHighKHz = pDfs->DfsParameters[NvRmDfsClockId_System].MaxKHz;
-    else    
+    else
     {   // System high boundary must be above all AV low boundaries
         for (i = 1; i < NvRmDfsClockId_Num; i++)
         {
@@ -3215,7 +3215,7 @@ NvRmDfsSetEmcEnvelope(
 }
 
 NvError
-NvRmDfsSetTarget( 
+NvRmDfsSetTarget(
     NvRmDeviceHandle hRmDeviceHandle,
     NvU32 DfsFreqListCount,
     const NvRmFreqKHz* pDfsTargetFreqList)
@@ -3303,14 +3303,14 @@ NvRmDfsGetClockUtilization(
     pClockUsage->LowCornerKHz = pDfs->LowCornerKHz.Domains[ClockId];
     pClockUsage->HighCornerKHz = pDfs->HighCornerKHz.Domains[ClockId];
     pClockUsage->CurrentKHz = pDfs->CurrentKHz.Domains[ClockId];
-    pClockUsage->AverageKHz = pDfs->Samplers[ClockId].AverageKHz; 
+    pClockUsage->AverageKHz = pDfs->Samplers[ClockId].AverageKHz;
 
     NvOsIntrMutexUnlock(pDfs->hIntrMutex);
     return NvSuccess;
 }
 
 NvError
-NvRmDfsGetProfileData( 
+NvRmDfsGetProfileData(
     NvRmDeviceHandle hRmDeviceHandle,
     NvU32 DfsProfileCount,
     NvU32* pSamplesNoList,
@@ -3370,7 +3370,7 @@ NvRmDfsLogStart(NvRmDeviceHandle hRmDeviceHandle)
     pDfs->SamplingWindow.CumulativeLogMs = 0;
     pDfs->SamplingWindow.CumulativeLp2TimeMs = 0;
     pDfs->SamplingWindow.CumulativeLp2Entries = 0;
-    
+
 #if DFS_LOGGING_SECONDS
     s_DfsLogWrIndex = 0;
     s_DfsLogStarvationWrIndex = 0;
@@ -3410,7 +3410,7 @@ NvRmDfsLogGetMeanFrequencies(
     msec = pDfs->SamplingWindow.CumulativeLogMs;
     for (i = 1; i < LogMeanFreqListCount; i++)
     {
-        pLogMeanFreqList[i] = 
+        pLogMeanFreqList[i] =
             (NvU32)NvDiv64(pDfs->Samplers[i].CumulativeLogCycles, msec);
     }
     // TODO: update if condition SystemKHz = AvpKHz changes
@@ -3426,7 +3426,7 @@ NvRmDfsLogGetMeanFrequencies(
 }
 
 NvError
-NvRmDfsLogActivityGetEntry( 
+NvRmDfsLogActivityGetEntry(
     NvRmDeviceHandle hRmDeviceHandle,
     NvU32 EntryIndex,
     NvU32 LogDomainsCount,
@@ -3484,7 +3484,7 @@ NvRmDfsLogActivityGetEntry(
 }
 
 NvError
-NvRmDfsLogStarvationGetEntry( 
+NvRmDfsLogStarvationGetEntry(
     NvRmDeviceHandle hRmDeviceHandle,
     NvU32 EntryIndex,
     NvU32* pSampleIndex,
@@ -3532,7 +3532,7 @@ NvRmDfsLogStarvationGetEntry(
 }
 
 NvError
-NvRmDfsLogBusyGetEntry( 
+NvRmDfsLogBusyGetEntry(
     NvRmDeviceHandle hRmDeviceHandle,
     NvU32 EntryIndex,
     NvU32* pSampleIndex,
@@ -3651,7 +3651,7 @@ NvRmDfsSetLowVoltageThreshold(
 /*****************************************************************************/
 
 NvError
-NvRmDiagGetTemperature( 
+NvRmDiagGetTemperature(
     NvRmDeviceHandle hRmDeviceHandle,
     NvRmTmonZoneId ZoneId,
     NvS32* pTemperatureC)
@@ -3674,5 +3674,3 @@ NvRmDiagGetTemperature(
             return NvError_NotSupported;
     }
 }
-
-/*****************************************************************************/
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c
index 4504b8a01819..623d475a5e75 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_transport.c
@@ -205,12 +205,12 @@ typedef struct NvRmTransportRec
     NvU32               RemotePort;
 
     // save a copy of the rm handle.
-    NvRmDeviceHandle hRmDevice; 
+    NvRmDeviceHandle hRmDevice;
 
     struct NvRmTransportRec *pNext;
 
     // unlikely to be used members at the end
-    
+
     // to be signalled when someone waits for a connector.
     NvOsSemaphoreHandle hOnConnectSem;
 
@@ -380,7 +380,7 @@ HandleConnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
     char PortName[MAX_PORT_NAME_LENGTH+1];
     NvU32 RemotePort;
     NvRmTransportHandle hPort;
-    
+
     RemotePort = pMessage[1];
     NvOsMemcpy(PortName, (void*)&pMessage[2], MAX_PORT_NAME_LENGTH);
     PortName[MAX_PORT_NAME_LENGTH] = 0;
@@ -416,7 +416,7 @@ HandleConnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
  *  [ Local Handle ]
  *
  * Response:
- *   [ Local Handle ] <- 0 
+ *   [ Local Handle ] <- 0
  */
 static void
 HandleDisconnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
@@ -443,7 +443,7 @@ HandleDisconnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
  *  [ Message ]
  *
  * Response:
- *   [ Message Length ] <- NvSuccess 
+ *   [ Message Length ] <- NvSuccess
  *   [ Transport Command ] <- When we can accept a new message
  */
 
@@ -472,7 +472,7 @@ HandlePortMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
     // !!! For sanity we should walk the list of open ports to make sure this is a valid port!
     // Queue the message even if in the open state as presumably this should only have happened if
     // due to a race condition with the transport connected messages.
-    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))    
+    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))
     {
         bSuccess = InsertMessage(hPort, (NvU8*)&pMessage[3], MessageLength);
         if (bSuccess)
@@ -488,11 +488,11 @@ HandlePortMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
     }
 }
 
-static void 
+static void
 HandleAVPResetMessage(NvRmDeviceHandle hDevice)
 {
     NvRmTransportHandle hPort;
-    
+
     hPort = FindPort(hDevice,(char*)"RPC_CPU_PORT");
     if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))
     {
@@ -566,7 +566,7 @@ InboxFullIsr(void *args)
     case  TransportCmd_Connect:
         HandleConnectMessage(hDevice, pMessage);
         break;
-        
+
     case  TransportCmd_Disconnect:
         HandleDisconnectMessage(hDevice, pMessage);
         break;
@@ -574,7 +574,7 @@ InboxFullIsr(void *args)
     case TransportCmd_Message:
         HandlePortMessage(hDevice, pMessage);
         break;
-            
+
     default:
         NV_ASSERT(0);
     }
@@ -643,7 +643,7 @@ RegisterTransportInterrupt(NvRmDeviceHandle hDevice)
      * one interrupt i.e. InboxFullIsr  */
     DmaIntHandlers[0] = InboxFullIsr;
     DmaIntHandlers[1] = OutboxEmptyIsr;
-    return NvRmInterruptRegister(hDevice, 1, IrqList, DmaIntHandlers, 
+    return NvRmInterruptRegister(hDevice, 1, IrqList, DmaIntHandlers,
             hDevice, &s_TransportInterruptHandle, NV_TRUE);
 }
 
@@ -685,7 +685,7 @@ NvRmPrivTransportAllocBuffers(NvRmDeviceHandle hRmDevice)
     }
     else
     {
-        s_TransportInfo.pReceiveMem  = (void *) (((NvUPtr)s_TransportInfo.pTransmitMem) + 
+        s_TransportInfo.pReceiveMem  = (void *) (((NvUPtr)s_TransportInfo.pTransmitMem) +
                                                               MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE);
     }
 
@@ -695,7 +695,7 @@ NvRmPrivTransportAllocBuffers(NvRmDeviceHandle hRmDevice)
 
     NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.MessageMemPhysAddr);
     return;
-    
+
 
 fail:
     NvRmMemHandleFree(hNewMemHandle);
@@ -727,12 +727,12 @@ NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
 
     NvOsMemset(&s_TransportInfo, 0, sizeof(s_TransportInfo));
     s_TransportInfo.hDevice = hRmDevice;
-   
+
     err = NvOsMutexCreate(&s_TransportInfo.mutex);
     if (err)
         goto fail;
 
-#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
     err = NvRmPrivXpcCreate(hRmDevice, &s_TransportInfo.hXpc);
     if (err)
         goto fail;
@@ -751,7 +751,7 @@ NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
     {
         NvU32             TimerAddr;
         NvU32             TimerSize;
-        
+
         NvRmModuleGetBaseAddress(hRmDevice, NvRmModuleID_TimerUs, &TimerAddr, &TimerSize);
         // map the us counter
         err = NvRmPhysicalMemMap(TimerAddr, TimerSize, NVOS_MEM_READ_WRITE,
@@ -759,10 +759,10 @@ NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
         if (err)
             goto fail;
     }
-    
+
 #endif
 
-#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
     err = RegisterTransportInterrupt(hRmDevice);
     if (err)
         goto fail;
@@ -772,7 +772,7 @@ NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
 
 
 fail:
-#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
     NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
     NvRmPrivTransportFreeBuffers(hRmDevice);
 #endif
@@ -787,7 +787,7 @@ fail:
 void NvRmTransportDeInit(NvRmDeviceHandle hRmDevice)
 {
     // Unregister the interrupts.
-#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE 
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
     NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
     NvRmPrivTransportFreeBuffers(hRmDevice);
     NvRmInterruptUnregister(hRmDevice, s_TransportInterruptHandle);
@@ -832,7 +832,7 @@ static void
 DeletePort(NvRmDeviceHandle hRmDevice, const NvRmTransportHandle hPort)
 {
     // Pointer to the pointer alleviates all special cases in linked list walking.
-    // I wish I was clever enough to have figured this out myself. 
+    // I wish I was clever enough to have figured this out myself.
 
     NvRmTransportHandle *hIter;
 
@@ -903,9 +903,9 @@ NvRmTransportOpen(
 
     // check if this is one of the special RPC ports used by the rm
     if ( NvOsStrcmp(pPortName, "RPC_AVP_PORT") == 0)
-    {        
+    {
         //If someone else wants to open this port
-        //just return the one already created.        
+        //just return the one already created.
         if (hPartner)
         {
             hPort = hPartner;
@@ -959,7 +959,7 @@ NvRmTransportOpen(
 
 
     // !!! loopback info
-#if LOOPBACK_PROFILE 
+#if LOOPBACK_PROFILE
     if (NvOsStrcmp(hPort->PortName, "LOOPTEST") == 0)
         hPort->bLoopTest = 1;
 #endif
@@ -997,7 +997,7 @@ void NvRmTransportClose(NvRmTransportHandle hPort)
     // Look and see if this port exists anywhere.
     NV_ASSERT(hPort);
 
-    
+
     NvOsMutexLock(s_TransportInfo.mutex);
     DeletePort(hPort->hRmDevice, hPort);  // unlink this port
 
@@ -1024,7 +1024,7 @@ void NvRmTransportClose(NvRmTransportHandle hPort)
         // unlink this port from the other side of the connection.
         hPort->hConnectedPort->hConnectedPort = NULL;
     }
-    
+
     if (hPort->RemotePort)
     {
         RemoteMessage[0] = TransportCmd_Disconnect;
@@ -1078,7 +1078,7 @@ NvRmTransportWaitForConnect(
         NvOsMutexUnlock(s_TransportInfo.mutex);
         goto exit_gracefully;
     }
-    
+
     hPort->hOnConnectSem = hSem;
     hPort->State = PortState_Waiting;
     NvOsMutexUnlock(s_TransportInfo.mutex);
@@ -1161,7 +1161,7 @@ NvRmPrivTransportWaitResponse(NvRmDeviceHandle hDevice, NvU32 *response, NvU32 R
             CurrentTime = NvOsGetTimeMS();
         }
     }
-    
+
     if ( pXpcMessage && GotResponse )
     {
         err = NvSuccess;
@@ -1234,9 +1234,9 @@ NvError NvRmTransportSendMsgInLP0(NvRmTransportHandle hPort,
     MessageHdr[0] = TransportCmd_Message;
     MessageHdr[1] = hPort->RemotePort;
     MessageHdr[2] = MessageSize;
-   
+
     ReadData = ((volatile NvU32*)s_TransportInfo.pTransmitMem)[0];
-    
+
     // Check for clear to send
     if ( ReadData != 0)
         return NvError_TransportMessageBoxFull;  // someone else is sending a message
@@ -1283,7 +1283,7 @@ NvError NvRmTransportConnect(NvRmTransportHandle hPort, NvU32 TimeoutMS)
     NvU32               CurrentTime;
     NvU32               ConnectMessage[ MAX_PORT_NAME_LENGTH/4 + 3];
     NvError             err;
-    
+
 
     // Look and see if there is a local port with the same name that is currently waiting, if there is
     // mark both ports as connected.
@@ -1319,7 +1319,7 @@ NvError NvRmTransportConnect(NvRmTransportHandle hPort, NvU32 TimeoutMS)
             ConnectMessage[0] = TransportCmd_Connect;
             ConnectMessage[1] = (NvU32)hPort;
             NvOsMemcpy(&ConnectMessage[2], hPort->PortName, MAX_PORT_NAME_LENGTH);
-            
+
             err = NvRmPrivTransportSendMessage(hPort->hRmDevice,
                       ConnectMessage, sizeof(ConnectMessage), NULL, 0);
             if (!err)
@@ -1356,7 +1356,7 @@ NvError NvRmTransportConnect(NvRmTransportHandle hPort, NvU32 TimeoutMS)
         CurrentTime = NvOsGetTimeMS();
         if ( (CurrentTime - StartTime) > TimeoutMS )
             return NvError_Timeout;
-        
+
         NvOsSleepMS(10);
     }
 
@@ -1401,7 +1401,7 @@ NvError NvRmTransportSetQueueDepth(
         {
             return NvSuccess;
         }
-        
+
         NV_ASSERT(!" Illegal meesage length or queue depth. ");
     }
 
@@ -1440,7 +1440,7 @@ NvRmPrivTransportSendRemoteMsg(
     MessageHdr[0] = TransportCmd_Message;
     MessageHdr[1] = hPort->RemotePort;
     MessageHdr[2] = MessageSize;
-   
+
     for (;;)
     {
         NvOsMutexLock(s_TransportInfo.mutex);
@@ -1502,7 +1502,7 @@ NvRmPrivTransportSendLocalMsg(
                 NvOsSemaphoreSignal(hRemotePort->hOnPushMsgSem);
             break;
         }
-        
+
         // The destination port is full.
         if (TimeoutMS == 0)
         {
@@ -1617,7 +1617,7 @@ NvRmTransportRecvMsg(
         NvOsMutexUnlock(s_TransportInfo.mutex);
         return NvError_TransportMessageBoxEmpty;
     }
-    
+
     ExtractMessage(hPort, (NvU8*)pMessageBuffer, pMessageSize, MaxSize);
     if (*pMessageSize > MaxSize)
     {
@@ -1637,7 +1637,7 @@ NvRmTransportRecvMsg(
         if (s_TransportInfo.pReceiveMem == NULL)
         {
             /* QT/EMUTRANS takes this path. */
-            NvRmMemRead(s_TransportInfo.hMessageMem, 
+            NvRmMemRead(s_TransportInfo.hMessageMem,
                         MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE,
                         TmpMessage,
                         MAX_MESSAGE_LENGTH);
@@ -1669,8 +1669,8 @@ NvRmTransportRecvMsg(
     return NvSuccess;
 }
 
-void 
-NvRmTransportGetPortName( 
+void
+NvRmTransportGetPortName(
     NvRmTransportHandle hPort,
     NvU8 *PortName,
     NvU32 PortNameSize )
@@ -1688,4 +1688,3 @@ NvRmTransportGetPortName(
 
     NvOsStrncpy((char *)PortName, hPort->PortName, PortNameSize);
 }
-
diff --git a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c
index c57d9cbe6666..eb26e852c892 100644
--- a/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c
+++ b/arch/arm/mach-tegra/nvrm/io/ap15/ap15rm_slink_hw_private.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -66,7 +66,7 @@
 
 static void
 SlinkHwSetSignalMode(
-    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwRegisters *pSlinkHwRegs,
     NvOdmQuerySpiSignalMode SignalMode);
 
 /**
@@ -74,7 +74,7 @@ SlinkHwSetSignalMode(
  */
 static void
 SlinkHwRegisterInitialize(
-    NvU32 SlinkInstanceId, 
+    NvU32 SlinkInstanceId,
     SerialHwRegisters *pSlinkHwRegs)
 {
     NvU32 CommandReg1;
@@ -93,7 +93,7 @@ SlinkHwRegisterInitialize(
     pSlinkHwRegs->IsHwChipSelectSupported = NV_FALSE;
 
     CommandReg1 = NV_RESETVAL(SLINK, COMMAND);
-    
+
     // Initialize the chip select bits to select the s/w only
     CommandReg1 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND, CS_SW, SOFT, CommandReg1);
 
@@ -123,7 +123,7 @@ SlinkHwRegisterInitialize(
  */
 static void
 SlinkHwSetSignalMode(
-    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwRegisters *pSlinkHwRegs,
     NvOdmQuerySpiSignalMode SignalMode)
 {
     NvU32 CommandReg = pSlinkHwRegs->HwRegs.SlinkRegs.Command1;
@@ -178,7 +178,7 @@ SlinkHwSetSignalMode(
  */
 static void
 SlinkHwSetChipSelectDefaultLevelFxn(
-    SerialHwRegisters *pHwRegs, 
+    SerialHwRegisters *pHwRegs,
     NvU32 ChipSelectId,
     NvBool IsHigh)
 {
@@ -190,7 +190,7 @@ SlinkHwSetChipSelectDefaultLevelFxn(
  */
 static void
 SlinkHwSetChipSelectLevel(
-    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwRegisters *pSlinkHwRegs,
     NvU32 ChipSelectId,
     NvBool IsHigh)
 {
@@ -208,28 +208,28 @@ SlinkHwSetChipSelectLevel(
         case 0:
             CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS0, CommandReg2);
             break;
-        
+
         case 1:
             CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS1, CommandReg2);
             break;
-        
+
         case 2:
             CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS2, CommandReg2);
             break;
-        
+
         case 3:
             CommandReg2 = NV_FLD_SET_DRF_DEF(SLINK, COMMAND2, SS_EN, CS3, CommandReg2);
             break;
-        
+
         default:
             NV_ASSERT(!"Invalid ChipSelectId");
-    }     
+    }
     pSlinkHwRegs->HwRegs.SlinkRegs.Command1 = CommandReg1;
     pSlinkHwRegs->HwRegs.SlinkRegs.Command2 = CommandReg2;
 
-    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2, 
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND2,
                             pSlinkHwRegs->HwRegs.SlinkRegs.Command2);
-    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND, 
+    SLINK_REG_WRITE32(pSlinkHwRegs->pRegsBaseAdd, COMMAND,
                             pSlinkHwRegs->HwRegs.SlinkRegs.Command1);
 }
 
@@ -242,7 +242,7 @@ SlinkHwSetChipSelectLevel(
  */
 static NvBool
 SlinkHwSetChipSelectLevelBasedOnPacket(
-    SerialHwRegisters *pSlinkHwRegs, 
+    SerialHwRegisters *pSlinkHwRegs,
     NvU32 ChipSelectId,
     NvBool IsHigh,
     NvU32 PacketRequested,
@@ -269,8 +269,8 @@ SlinkHwSetCsSetupHoldTime(
  */
 static NvU32
 SlinkHwWriteInTransmitFifo(
-    SerialHwRegisters *pSlinkHwRegs, 
-    NvU32 *pTxBuff,  
+    SerialHwRegisters *pSlinkHwRegs,
+    NvU32 *pTxBuff,
     NvU32 WordRequested)
 {
     NvU32 WordWritten = 0;
@@ -288,12 +288,12 @@ SlinkHwWriteInTransmitFifo(
 
 /**
  * Read the data from the receive fifo.
- * Returns the number of words it read.   
+ * Returns the number of words it read.
  */
 static NvU32
 SlinkHwReadFromReceiveFifo(
-    SerialHwRegisters *pSlinkHwRegs, 
-    NvU32 *pRxBuff,  
+    SerialHwRegisters *pSlinkHwRegs,
+    NvU32 *pRxBuff,
     NvU32 WordRequested)
 {
     NvU32 WordsRemaining = WordRequested;
@@ -320,4 +320,3 @@ void NvRmPrivSpiSlinkInitSlinkInterface_v1_0(HwInterface *pSlinkInterface)
     pSlinkInterface->HwWriteInTransmitFifoFxn = SlinkHwWriteInTransmitFifo;
     pSlinkInterface->HwReadFromReceiveFifoFxn =  SlinkHwReadFromReceiveFifo;
 }
-
diff --git a/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpio.c b/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpio.c
index f070b87fb379..672522cfc9be 100644
--- a/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpio.c
+++ b/arch/arm/mach-tegra/nvrm/io/common/nvrm_gpio.c
@@ -118,7 +118,7 @@ NvError NvRmGpioAcquirePinHandle(NvRmGpioHandle gpio, NvU32 nr_port,
 	char gpio_name[12];
 	int ret;
 
-#if CONFIG_ARCH_TEGRA_2x_SOC
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
 	if (nr_port == NVRM_GPIO_CAMERA_PORT) {
 		if (nr_pin>=0 && nr_pin<=4) {
 			nr_gpio = TEGRA_GPIO_PBB1 + nr_pin;
@@ -130,7 +130,7 @@ NvError NvRmGpioAcquirePinHandle(NvRmGpioHandle gpio, NvU32 nr_port,
 			pr_err("%s: invalid cam gpio %u\n", __func__, nr_pin);
 			return NvError_BadParameter;
 		}
-	} else 
+	} else
 #endif
 	{
 		nr_gpio = nr_port*8 + nr_pin;
@@ -268,7 +268,6 @@ NvError NvRmGpioConfigPins(NvRmGpioHandle gpio, NvRmGpioPinHandle *hpins,
 			default:
 				break;
 			}
-			
 		}
 	}
author	Scott Williams <scwilliams@nvidia.com>	2010-06-21 16:51:30 -0700
committer	Gary King <gking@nvidia.com>	2010-06-22 09:50:46 -0700
commit	7965e62aa8528e621a1d1c6503de33b91826cc98 (patch)
tree	3b276ffbf4f84a6ef646f214770d7e80be16061c /arch
parent	d81df22941c19ac21e9da751fd8d1835bab9a834 (diff)