diff options
| author | Peter Chen <peter.chen@freescale.com> | 2013-11-18 09:24:08 +0800 |
|---|---|---|
| committer | Anthony Felice <tony.felice@timesys.com> | 2014-01-16 15:52:27 -0500 |
| commit | ce924a53db49cb570f7b481981d488ba8e270828 (patch) | |
| tree | b3a0d0017e9aae4606fd6fe304a54a09b0066aaa /arch | |
| parent | 65321fcd82b5c0dcb7c86f3d1e9b6b249c7b23ba (diff) | |
usb: certification: several fixes
- change PHY TX/RX parameters accoording to Richard's email
- Disable OTG descripor
- Add Freescale VID/PID
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mvf/usb_dr.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-mvf/usb_dr2.c | 12 |
2 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-mvf/usb_dr.c b/arch/arm/mach-mvf/usb_dr.c index bbd29f3b45a9..c063193364d1 100644 --- a/arch/arm/mach-mvf/usb_dr.c +++ b/arch/arm/mach-mvf/usb_dr.c @@ -90,6 +90,7 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) u32 tmp; void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY0_BASE_ADDR); void __iomem *phy_ctrl; + void __iomem *phy_param; /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; @@ -115,6 +116,17 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) /* Power up the PHY */ __raw_writel(0, phy_reg + HW_USBPHY_PWD); + /* + * For USB Certification + * TX: set edge rate to max, increase the amplitude + * with 2 steps (Level = ~ 437 mV). + * RX: reduce transmission envelope detector level with about 20 mV + */ + phy_param = phy_reg + HW_USBPHY_TX; + __raw_writel(0x1c060605, phy_param); + phy_param = phy_reg + HW_USBPHY_RX; + __raw_writel(0x1, phy_param); + return 0; } /* Notes: configure USB clock*/ diff --git a/arch/arm/mach-mvf/usb_dr2.c b/arch/arm/mach-mvf/usb_dr2.c index 67e3fcdbc921..8a83ac1ea360 100644 --- a/arch/arm/mach-mvf/usb_dr2.c +++ b/arch/arm/mach-mvf/usb_dr2.c @@ -85,6 +85,7 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) u32 tmp; void __iomem *phy_reg = MVF_IO_ADDRESS(MVF_USBPHY1_BASE_ADDR); void __iomem *phy_ctrl; + void __iomem *phy_param; /* Stop then Reset */ UOG2_USBCMD &= ~UCMD_RUN_STOP; @@ -117,6 +118,17 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) phy_reg + HW_USBPHY_CTRL_SET); } + /* + * For USB Certification + * TX: set edge rate to max, increase the amplitude + * with 2 steps (Level = ~ 437 mV). + * RX: reduce transmission envelope detector level with about 20 mV + */ + phy_param = phy_reg + HW_USBPHY_TX; + __raw_writel(0x1c060605, phy_param); + phy_param = phy_reg + HW_USBPHY_RX; + __raw_writel(0x1, phy_param); + return 0; } /* Notes: configure USB clock*/ |