diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-09-16 07:28:43 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-09-16 07:28:43 +0200 |
| commit | f7b222893aa4c464c3ef2fba778b1aa68ffb09a5 (patch) | |
| tree | d4e641bed67bbd87d43b748a615e5f6b8bfc3e51 /arch | |
| parent | 01e50c593e2dc6baae3aeeb12bc9167a1c60dce7 (diff) | |
mvf: clock: fix DCU clock rounding
Fix rounding in the DCU clocking which previously made it impossible to
actually set a clock that did not divide to a whole number (e.g.
150666666 Hz from the 452 MHz PFD2 parent clock).
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mvf/clock.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c index 5ac0ff1766fb..d06382b1eb93 100644 --- a/arch/arm/mach-mvf/clock.c +++ b/arch/arm/mach-mvf/clock.c @@ -1,4 +1,3 @@ - /* * Copyright 2012 Freescale Semiconductor, Inc. * @@ -1339,7 +1338,7 @@ static int _clk_dcu0_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); - div = (parent_rate + rate - 1) / rate; + div = parent_rate / rate; if (div == 0) div++; if (((parent_rate / div) != rate) || (div > 8)) |