diff options
| author | Jun Li <r65092@freescale.com> | 2009-12-02 15:08:48 +0800 |
|---|---|---|
| committer | Jun Li <r65092@freescale.com> | 2009-12-03 18:18:37 +0800 |
| commit | be1bbd8525e6a5d8f182dadadcb6ff9513986a66 (patch) | |
| tree | 2da5c91b2aa95f906d731975005a79e3401c5883 /arch | |
| parent | 898a2a3fc5527276e96468058c371bb7604930c0 (diff) | |
ENGR00116829 close usbpll for usb controler is not in serial mode.
1. close usb_clk after usb otg controller switch to utmi mode.
2. usb_clk is a glabal variable for 60M usbpll, when enable usboh3_clk
for i.MX51 host port, usb_clk is used, which causes usb_clk can not be
closed after the controller is in ULPI mode.
Signed-off-by: Li Jun <r65092@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/plat-mxc/usb_common.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c index c6551a5c26af..18ea2a6caab8 100644 --- a/arch/arm/plat-mxc/usb_common.c +++ b/arch/arm/plat-mxc/usb_common.c @@ -453,9 +453,9 @@ int fsl_usb_host_init(struct platform_device *pdev) } if (cpu_is_mx51()) { - usb_clk = clk_get(NULL, "usboh3_clk"); - clk_enable(usb_clk); - clk_put(usb_clk); + struct clk *usboh3_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usboh3_clk); + clk_put(usboh3_clk); } /* enable board power supply for xcvr */ @@ -745,15 +745,14 @@ static void otg_set_utmi_xcvr(void) */ msleep(100); - /* Turn off the usbpll for mx25 UTMI tranceivers */ - /* DDD: can we do this UTMI xcvrs on all boards? */ - if (cpu_is_mx25()) { - clk_disable(usb_clk); - } else if (cpu_is_mx37()) { + if (cpu_is_mx37()) { /* fix USB PHY Power Gating leakage issue for i.MX37 */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; } + + /* Turn off the usbpll for UTMI tranceivers */ + clk_disable(usb_clk); } static int otg_used = 0; |