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authorSean Cross <xobs@kosagi.com>2013-09-26 10:51:09 +0800
committerRichard Zhu <r65037@freescale.com>2013-11-20 14:10:26 +0800
commit9dceff57c161451785a05a8a230725c480ee6798 (patch)
tree8be685c70631e418c549efaa2f3b7c0f1cba198b /arch
parentadaacb0f426a5a80cdf13874e9e779d745960107 (diff)
ARM: dts: imx6qdl: add pcie device node
Add pcie device node for imx6qdl. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> (cherry picked from commit 3a57291fa4ca7f7647d826f5b47082ef306d839f)
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 3ee2b5ee2a5f..c2f7fd5af550 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -117,6 +117,22 @@
arm,data-latency = <4 2 3>;
};
+ pcie: pcie@0x01000000 {
+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
+ reg = <0x01ffc000 0x4000>; /* DBI */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
+ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <0 123 0x04>;
+ clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
+ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
+ status = "disabled";
+ };
+
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 0x04>;