ARM: Tegra: TN7C:clean up board info

there is just one board id(P1988), clean up useless board info
detection. there is just one Fab version A00 so far, also remove useless
fab version checking.

Bug 1430589

Signed-off-by: David Pu <dpu@nvidia.com>
Change-Id: I314173117d5620ce53770fcc2c18e29d39fa782d
Reviewed-on: http://git-master/r/354893
Reviewed-by: Danny Song <dsong@nvidia.com>
Tested-by: Danny Song <dsong@nvidia.com>

9 files changed, 53 insertions, 2718 deletions

diff --git a/arch/arm/mach-tegra/board-tegranote7c-kbc.c b/arch/arm/mach-tegra/board-tegranote7c-kbc.c
index 85847ee0c8c0..67fea53d1736 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-kbc.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-kbc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -54,21 +54,7 @@
 		.debounce_interval = 0,             \
 	}
 
-static struct gpio_keys_button tegranote7c_e1569_keys[] = {
-	[0] = GPIO_KEY(KEY_POWER, PQ0, 1),
-	[1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
-	[2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0),
-};
-
-static struct gpio_keys_button tegranote7c_p1640_keys[] = {
-	[0] = GPIO_KEY(KEY_POWER, PQ0, 1),
-	[1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
-	[2] = GPIO_KEY(KEY_VOLUMEDOWN, PQ2, 0),
-	[3] = GPIO_SW(SW_LID, PC7, 1, 1),
-	[4] = GPIO_SW(SW_TABLET_MODE, PQ1, 0, 0),
-};
-
-static struct gpio_keys_button tegranote7c_p1640_a01_keys[] = {
+static struct gpio_keys_button tegranote7c_p1988_keys[] = {
 	[0] = GPIO_KEY(KEY_POWER, PQ0, 1),
 	[1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0),
 	[2] = GPIO_KEY(KEY_VOLUMEDOWN, PQ2, 0),
@@ -95,8 +81,8 @@ static int tegranote7c_wakeup_key(void)
 }
 
 static struct gpio_keys_platform_data tegranote7c_keys_pdata = {
-	.buttons	= tegranote7c_e1569_keys,
-	.nbuttons	= ARRAY_SIZE(tegranote7c_e1569_keys),
+	.buttons	= tegranote7c_p1988_keys,
+	.nbuttons	= ARRAY_SIZE(tegranote7c_p1988_keys),
 	.wakeup_key	= tegranote7c_wakeup_key,
 };
 
@@ -110,24 +96,7 @@ static struct platform_device tegranote7c_keys_device = {
 
 int __init tegranote7c_kbc_init(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988) {
-		if (board_info.fab == BOARD_FAB_A00) {
-			tegranote7c_keys_pdata.buttons = tegranote7c_p1640_keys;
-			tegranote7c_keys_pdata.nbuttons =
-			   ARRAY_SIZE(tegranote7c_p1640_keys);
-		} else {
-			tegranote7c_keys_pdata.buttons = tegranote7c_p1640_a01_keys;
-			tegranote7c_keys_pdata.nbuttons =
-			   ARRAY_SIZE(tegranote7c_p1640_a01_keys);
-		}
-	}
-
 	platform_device_register(&tegranote7c_keys_device);
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-tegra/board-tegranote7c-memory.c b/arch/arm/mach-tegra/board-tegranote7c-memory.c
index 430b78f9102b..438603321caa 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-memory.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-memory.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -26,2166 +26,7 @@
 #include "fuse.h"
 #include "devices.h"
 
-static struct tegra11_emc_table e1569_mt41k128m16_125_table[] = {
-	{
-		0x41,       /* Rev 4.0.3 */
-		12750,      /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x4000003e, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000000, /* EMC_RC */
-			0x00000003, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000000, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000060, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000007, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000005, /* EMC_TXSR */
-			0x00000005, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000001, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000064, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x40040001, /* MC_EMEM_ARB_CFG */
-			0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x77e30303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000007, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		57820,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		20400,      /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000026, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000000, /* EMC_RC */
-			0x00000003, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000000, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x0000009a, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000007, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000005, /* EMC_TXSR */
-			0x00000006, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000001, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x000000a0, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x40020001, /* MC_EMEM_ARB_CFG */
-			0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x75430303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		35610,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		40800,      /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000012, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000001, /* EMC_RC */
-			0x00000006, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000001, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000134, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000007, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000007, /* EMC_TXSR */
-			0x0000000c, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000002, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x0000013f, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0xa0000001, /* MC_EMEM_ARB_CFG */
-			0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x73630303, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000015, /* MC_PTSA_GRANT_DECREMENT */
-			0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		20850,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		68000,      /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x4000000a, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000003, /* EMC_RC */
-			0x0000000a, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000002, /* EMC_RAS */
-			0x00000000, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000000, /* EMC_RD_RCD */
-			0x00000000, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000202, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000008, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x0000000c, /* EMC_TXSR */
-			0x00000013, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000003, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000213, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x00000001, /* MC_EMEM_ARB_CFG */
-			0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
-			0x72c30403, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000023, /* MC_PTSA_GRANT_DECREMENT */
-			0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		10720,      /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		102000,     /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000006, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000004, /* EMC_RC */
-			0x00000010, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000003, /* EMC_RAS */
-			0x00000001, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000001, /* EMC_RD_RCD */
-			0x00000001, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000303, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000000d, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000012, /* EMC_TXSR */
-			0x0000001c, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000005, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x0000031c, /* EMC_TREFBW */
-			0x00000005, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x08000001, /* MC_EMEM_ARB_CFG */
-			0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
-			0x72830504, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000006, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000034, /* MC_PTSA_GRANT_DECREMENT */
-			0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		6890,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		204000,     /* SDRAM frequency */
-		900,        /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000002, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000009, /* EMC_RC */
-			0x00000020, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000007, /* EMC_RAS */
-			0x00000002, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x0000000a, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x0000000b, /* EMC_W2P */
-			0x00000002, /* EMC_RD_RCD */
-			0x00000002, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000006, /* EMC_IBDLY */
-			0x00010000, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000607, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x00000002, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000001d, /* EMC_AR2PDEN */
-			0x0000000f, /* EMC_RW2PDEN */
-			0x00000023, /* EMC_TXSR */
-			0x00000038, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000009, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000638, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000aa88, /* EMC_FBIO_CFG5 */
-			0x000000a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0006c000, /* EMC_DLL_XFORM_DQS4 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS5 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS6 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000a11c, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x05057404, /* EMC_XM2VTTGENPADCTRL */
-			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT */
-			0x000c000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x01000003, /* MC_EMEM_ARB_CFG */
-			0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030102, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
-			0x72440a06, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000004, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0006c000, /* EMC_DLL_XFORM_DQS0 */
-			0x00000009, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x0079e79e, /* EMC_XM2DQSPADCTRL4 */
-			0x20820800, /* EMC_XM2DQSPADCTRL3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000808, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS1 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS2 */
-			0x0006c000, /* EMC_DLL_XFORM_DQS3 */
-			0x00048000, /* EMC_DLL_XFORM_DQ1 */
-			0x00048000, /* EMC_DLL_XFORM_DQ2 */
-			0x00048000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000068, /* MC_PTSA_GRANT_DECREMENT */
-			0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x7320000e, /* EMC_CFG */
-		0x80001221, /* Mode Register 0 */
-		0x80100003, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		3420,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		312000,     /* SDRAM frequency */
-		1000,       /* min voltage */
-		"pll_c",    /* clock source id */
-		0x24000002, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x0000000e, /* EMC_RC */
-			0x00000030, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000009, /* EMC_RAS */
-			0x00000003, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x00000008, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x00000009, /* EMC_W2P */
-			0x00000003, /* EMC_RD_RCD */
-			0x00000003, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x00000004, /* EMC_WDV_MASK */
-			0x00000007, /* EMC_IBDLY */
-			0x00080006, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000d, /* EMC_RDV_MASK */
-			0x00000945, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000002e, /* EMC_AR2PDEN */
-			0x0000000e, /* EMC_RW2PDEN */
-			0x00000036, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x0000000d, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000986, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00030000, /* EMC_DLL_XFORM_DQS4 */
-			0x00030000, /* EMC_DLL_XFORM_DQS5 */
-			0x00030000, /* EMC_DLL_XFORM_DQS6 */
-			0x00030000, /* EMC_DLL_XFORM_DQS7 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0190000c, /* EMC_MRS_WAIT_CNT */
-			0x0190000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0b000004, /* MC_EMEM_ARB_CFG */
-			0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000007, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
-			0x76e50f08, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00030000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000b, /* EMC_QSAFE */
-			0x00028000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00030000, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00024000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00024000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00024000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS1 */
-			0x00030000, /* EMC_DLL_XFORM_DQS2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS3 */
-			0x00030000, /* EMC_DLL_XFORM_DQ1 */
-			0x00030000, /* EMC_DLL_XFORM_DQ2 */
-			0x00030000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00030000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000b, /* EMC_QSAFE */
-			0x00028000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000d, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00030000, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00024000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00024000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00024000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS1 */
-			0x00030000, /* EMC_DLL_XFORM_DQS2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS3 */
-			0x00030000, /* EMC_DLL_XFORM_DQ1 */
-			0x00030000, /* EMC_DLL_XFORM_DQ2 */
-			0x00030000, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00028000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000000a0, /* MC_PTSA_GRANT_DECREMENT */
-			0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x5320000e, /* EMC_CFG */
-		0x80000321, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200000, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		2680,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		408000,     /* SDRAM frequency */
-		1000,       /* min voltage */
-		"pll_p",    /* clock source id */
-		0x40000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000012, /* EMC_RC */
-			0x00000040, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x0000000d, /* EMC_RAS */
-			0x00000004, /* EMC_RP */
-			0x00000005, /* EMC_R2W */
-			0x00000009, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000c, /* EMC_W2P */
-			0x00000004, /* EMC_RD_RCD */
-			0x00000004, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000004, /* EMC_WDV */
-			0x00000004, /* EMC_WDV_MASK */
-			0x00000007, /* EMC_IBDLY */
-			0x00080006, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000004, /* EMC_QRST */
-			0x0000000e, /* EMC_RDV_MASK */
-			0x00000c2f, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000003d, /* EMC_AR2PDEN */
-			0x00000011, /* EMC_RW2PDEN */
-			0x00000046, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000011, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000004, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000c70, /* EMC_TREFBW */
-			0x00000006, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0x002c0080, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00018000, /* EMC_DLL_XFORM_DQS4 */
-			0x00018000, /* EMC_DLL_XFORM_DQS5 */
-			0x00018000, /* EMC_DLL_XFORM_DQS6 */
-			0x00018000, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0001013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x03035504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0181000c, /* EMC_MRS_WAIT_CNT */
-			0x0181000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80001944, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x02000006, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
-			0x7547130b, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00018000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00020001, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000005, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000005, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000005, /* EMC_DLL_XFORM_ADDR2 */
-			0x00018000, /* EMC_DLL_XFORM_DQS1 */
-			0x00018000, /* EMC_DLL_XFORM_DQS2 */
-			0x00018000, /* EMC_DLL_XFORM_DQS3 */
-			0x00020001, /* EMC_DLL_XFORM_DQ1 */
-			0x00020001, /* EMC_DLL_XFORM_DQ2 */
-			0x00020001, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000004, /* EMC_FBIO_CFG6 */
-			0x00000007, /* EMC_QUSE */
-			0x00000005, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x00018000, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x0000000e, /* EMC_RDV */
-			0x00208208, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00020001, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000005, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000000, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000005, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000005, /* EMC_DLL_XFORM_ADDR2 */
-			0x00018000, /* EMC_DLL_XFORM_DQS1 */
-			0x00018000, /* EMC_DLL_XFORM_DQS2 */
-			0x00018000, /* EMC_DLL_XFORM_DQS3 */
-			0x00020001, /* EMC_DLL_XFORM_DQ1 */
-			0x00020001, /* EMC_DLL_XFORM_DQ2 */
-			0x00020001, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x000000d1, /* MC_PTSA_GRANT_DECREMENT */
-			0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200006, /* EMC_CFG */
-		0x80000731, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1750,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		528000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x80000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000018, /* EMC_RC */
-			0x00000053, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000010, /* EMC_RAS */
-			0x00000006, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x00000009, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x0000000d, /* EMC_W2P */
-			0x00000006, /* EMC_RD_RCD */
-			0x00000006, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x00000009, /* EMC_IBDLY */
-			0x00090007, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000007, /* EMC_QRST */
-			0x00000010, /* EMC_RDV_MASK */
-			0x00000fd8, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x0000000b, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000050, /* EMC_AR2PDEN */
-			0x00000012, /* EMC_RW2PDEN */
-			0x0000005a, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000004, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x00000016, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000005, /* EMC_TCLKSTABLE */
-			0x00000006, /* EMC_TCLKSTOP */
-			0x00001019, /* EMC_TREFBW */
-			0x00000008, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf0120091, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x07077504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x016e000c, /* EMC_MRS_WAIT_CNT */
-			0x016e000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80002066, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0f000007, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
-			0x7428180e, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000009, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000010, /* EMC_RDV */
-			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00010000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000909, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00010000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00010000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x00000009, /* EMC_QUSE */
-			0x00000007, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000010, /* EMC_RDV */
-			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x00010000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000909, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00010000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00010000, /* EMC_DLL_XFORM_ADDR2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
-			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000010e, /* MC_PTSA_GRANT_DECREMENT */
-			0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x73100004, /* EMC_CFG */
-		0x80000941, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200008, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1440,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		624000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_c",    /* clock source id */
-		0x24000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x0000001d, /* EMC_RC */
-			0x00000062, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000014, /* EMC_RAS */
-			0x00000007, /* EMC_RP */
-			0x00000007, /* EMC_R2W */
-			0x0000000b, /* EMC_W2R */
-			0x00000003, /* EMC_R2P */
-			0x00000010, /* EMC_W2P */
-			0x00000007, /* EMC_RD_RCD */
-			0x00000007, /* EMC_WR_RCD */
-			0x00000003, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000005, /* EMC_WDV */
-			0x00000005, /* EMC_WDV_MASK */
-			0x0000000a, /* EMC_IBDLY */
-			0x000c000a, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000007, /* EMC_QRST */
-			0x00000012, /* EMC_RDV_MASK */
-			0x000012c4, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000002, /* EMC_PDEX2WR */
-			0x0000000d, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000005e, /* EMC_AR2PDEN */
-			0x00000015, /* EMC_RW2PDEN */
-			0x0000006b, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000005, /* EMC_TCKE */
-			0x00000005, /* EMC_TCKESR */
-			0x00000005, /* EMC_TPD */
-			0x00000019, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000006, /* EMC_TCLKSTABLE */
-			0x00000007, /* EMC_TCLKSTOP */
-			0x00001305, /* EMC_TREFBW */
-			0x00000009, /* EMC_QUSE_EXTRA */
-			0x00000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf00d0191, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x007f800b, /* EMC_DLL_XFORM_DQS4 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS5 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS6 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc085, /* EMC_XM2CLKPADCTRL */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x07077504, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0160000c, /* EMC_MRS_WAIT_CNT */
-			0x0160000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x06000009, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
-			0x0000000f, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
-			0x07050202, /* MC_EMEM_ARB_DA_TURNS */
-			0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */
-			0x736a1d10, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000a, /* EMC_QUSE */
-			0x00000008, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x007f800b, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000012, /* EMC_RDV */
-			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00000009, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000909, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS1 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS2 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS3 */
-			0x00000009, /* EMC_DLL_XFORM_DQ1 */
-			0x00000009, /* EMC_DLL_XFORM_DQ2 */
-			0x00000009, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000a, /* EMC_QUSE */
-			0x00000008, /* EMC_EINPUT */
-			0x00000004, /* EMC_EINPUT_DURATION */
-			0x007f800b, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000c, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000012, /* EMC_RDV */
-			0x0028a28a, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x00000009, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000909, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS1 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS2 */
-			0x007f800b, /* EMC_DLL_XFORM_DQS3 */
-			0x00000009, /* EMC_DLL_XFORM_DQ1 */
-			0x00000009, /* EMC_DLL_XFORM_DQ2 */
-			0x00000009, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x0000013f, /* MC_PTSA_GRANT_DECREMENT */
-			0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x53200000, /* EMC_CFG */
-		0x80000b61, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200010, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1440,       /* expected dvfs latency (ns) */
-	},
-	{
-		0x41,       /* Rev 4.0.3 */
-		792000,     /* SDRAM frequency */
-		1100,       /* min voltage */
-		"pll_m",    /* clock source id */
-		0x80000000, /* CLK_SOURCE_EMC */
-		99,         /* number of burst_regs */
-		30,         /* number of trim_regs (each channel) */
-		11,         /* number of up_down_regs */
-		{
-			0x00000024, /* EMC_RC */
-			0x0000007d, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000019, /* EMC_RAS */
-			0x0000000a, /* EMC_RP */
-			0x00000009, /* EMC_R2W */
-			0x0000000d, /* EMC_W2R */
-			0x00000004, /* EMC_R2P */
-			0x00000013, /* EMC_W2P */
-			0x0000000a, /* EMC_RD_RCD */
-			0x0000000a, /* EMC_WR_RCD */
-			0x00000004, /* EMC_RRD */
-			0x00000001, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000006, /* EMC_WDV */
-			0x00000006, /* EMC_WDV_MASK */
-			0x0000000b, /* EMC_IBDLY */
-			0x000d000a, /* EMC_PUTERM_EXTRA */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000008, /* EMC_QRST */
-			0x00000014, /* EMC_RDV_MASK */
-			0x000017e4, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000003, /* EMC_PDEX2WR */
-			0x00000012, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x00000077, /* EMC_AR2PDEN */
-			0x00000018, /* EMC_RW2PDEN */
-			0x00000087, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000005, /* EMC_TCKE */
-			0x00000005, /* EMC_TCKESR */
-			0x00000005, /* EMC_TPD */
-			0x00000020, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000007, /* EMC_TCLKSTABLE */
-			0x00000008, /* EMC_TCLKSTOP */
-			0x00001825, /* EMC_TREFBW */
-			0x0000000a, /* EMC_QUSE_EXTRA */
-			0x80000020, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x0000ba88, /* EMC_FBIO_CFG5 */
-			0xf0070191, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00000008, /* EMC_DLL_XFORM_DQS4 */
-			0x00000008, /* EMC_DLL_XFORM_DQS5 */
-			0x00000008, /* EMC_DLL_XFORM_DQS6 */
-			0x00000008, /* EMC_DLL_XFORM_DQS7 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x001112a0, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x0000013d, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x77ffc084, /* EMC_XM2CLKPADCTRL */
-			0x81f1f508, /* EMC_XM2COMPPADCTRL */
-			0x07076604, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000000, /* EMC_TXDSRVTTGEN */
-			0x02000000, /* EMC_FBIO_SPARE */
-			0x00000802, /* EMC_CTT_TERM_CTRL */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0147000c, /* EMC_MRS_WAIT_CNT */
-			0x0147000c, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0x00000000, /* EMC_CTT */
-			0x00000000, /* EMC_CTT_DURATION */
-			0x80003018, /* EMC_DYN_SELF_REF_CONTROL */
-			0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
-			0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
-			0x0e00000b, /* MC_EMEM_ARB_CFG */
-			0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
-			0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
-			0x08060202, /* MC_EMEM_ARB_DA_TURNS */
-			0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
-			0x72cc2414, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000b, /* EMC_QUSE */
-			0x00000008, /* EMC_EINPUT */
-			0x00000006, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000014, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
-			0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000006, /* EMC_FBIO_CFG6 */
-			0x0000000b, /* EMC_QUSE */
-			0x00000008, /* EMC_EINPUT */
-			0x00000006, /* EMC_EINPUT_DURATION */
-			0x00000008, /* EMC_DLL_XFORM_DQS0 */
-			0x0000000d, /* EMC_QSAFE */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000014, /* EMC_RDV */
-			0x00249249, /* EMC_XM2DQSPADCTRL4 */
-			0x10410400, /* EMC_XM2DQSPADCTRL3 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
-			0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */
-			0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */
-			0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS1 */
-			0x00000008, /* EMC_DLL_XFORM_DQS2 */
-			0x00000008, /* EMC_DLL_XFORM_DQS3 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ1 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ2 */
-			0x007fc00a, /* EMC_DLL_XFORM_DQ3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-		},
-		{
-			0x00000196, /* MC_PTSA_GRANT_DECREMENT */
-			0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */
-			0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */
-			0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */
-			0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */
-			0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */
-			0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */
-			0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */
-			0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */
-			0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */
-			0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x73000000, /* EMC_CFG */
-		0x80000d71, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200218, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-		1200,       /* expected dvfs latency (ns) */
-	},
-};
-
-static struct tegra11_emc_table p1640_mt41k128m16_125_table[] = {
+static struct tegra11_emc_table p1988_mt41k128m16_125_table[] = {
 	{
 		0x42,       /* Rev 4.0.3 */
 		12750,      /* SDRAM frequency */
@@ -4158,30 +1999,15 @@ static struct tegra11_emc_table p1640_mt41k128m16_125_table[] = {
 	},
 };
 
-static struct tegra11_emc_pdata e1569_mt41k128m16_125_pdata = {
-	.description = "e1569_mt41k128m16_125",
-	.tables = e1569_mt41k128m16_125_table,
-	.num_tables = ARRAY_SIZE(e1569_mt41k128m16_125_table),
-};
-
-static struct tegra11_emc_pdata p1640_mt41k128m16_125_pdata = {
-	.description = "p1640_mt41k128m16_125",
-	.tables = p1640_mt41k128m16_125_table,
-	.num_tables = ARRAY_SIZE(p1640_mt41k128m16_125_table),
+static struct tegra11_emc_pdata p1988_mt41k128m16_125_pdata = {
+	.description = "p1988_mt41k128m16_125",
+	.tables = p1988_mt41k128m16_125_table,
+	.num_tables = ARRAY_SIZE(p1988_mt41k128m16_125_table),
 };
 
 static struct tegra11_emc_pdata *tegranote7c_get_emc_data(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_E1569)
-		return &e1569_mt41k128m16_125_pdata;
-	else if (board_info.board_id == BOARD_P1988)
-		return &p1640_mt41k128m16_125_pdata;
-	else
-		return NULL;
+	return &p1988_mt41k128m16_125_pdata;
 }
 
 int __init tegranote7c_emc_init(void)
diff --git a/arch/arm/mach-tegra/board-tegranote7c-power.c b/arch/arm/mach-tegra/board-tegranote7c-power.c
index 06f95962e304..381605ced966 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-power.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-power.c
@@ -617,19 +617,12 @@ FIXED_REG(9,   en_avdd_hdmi_pll,       en_avdd_hdmi_pll,
 	ADD_FIXED_REG(vddio_sd_slot),		\
 	ADD_FIXED_REG(vd_cam_1v8),
 
-#define E1569_FIXED_REG				\
-	ADD_FIXED_REG(dvdd_lcd_1v8),		\
-	ADD_FIXED_REG(dvdd_ts),
-
 #define P1988_FIXED_REG				\
+	ADD_FIXED_REG(dvdd_lcd_1v8),		\
+	ADD_FIXED_REG(dvdd_ts),                 \
 	ADD_FIXED_REG(en_lcd_1v8),              \
 	ADD_FIXED_REG(en_avdd_hdmi_pll)
 
-/* Gpio switch regulator platform data for TegraNote7C E1569 */
-static struct platform_device *fixed_reg_devs_e1569[] = {
-	TEGRANOTE7C_COMMON_FIXED_REG
-	E1569_FIXED_REG
-};
 
 /* Gpio switch regulator platform data for Tegranote7c */
 static struct platform_device *fixed_reg_devs_p1988[] = {
@@ -642,7 +635,6 @@ int __init tegranote7c_palmas_regulator_init(void)
 	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
 	u32 pmc_ctrl;
 	int i;
-	struct board_info board_info;
 
 	/* TPS65913: Normal state of INT request line is LOW.
 	 * configure the power management controller to trigger PMU
@@ -655,29 +647,19 @@ int __init tegranote7c_palmas_regulator_init(void)
 		pmic_platform.reg_init[i] = tegranote7c_reg_init[i];
 	}
 
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988 &&
-			((board_info.fab < BOARD_FAB_A04) ||
-			(board_info.fab >= BOARD_FAB_A04 &&
-			tegra_bct_strapping != 1))) {
-		/* Boot strapping 0, 2, 3 indicate Micron 1GB MT41K128M16-125
-		 * and it requires VDDIO_DDR 1.38V for stability.
-		 * Boot strapping 1 indicates Hynix 1GB H5TC2G63FFR-PBA and
-		 * it requires VDDIO_DDR 1.35V.
-		 */
-		tegranote7c_reg_data[PALMAS_REG_SMPS7]->constraints.min_uV =
-									1380000;
-		tegranote7c_reg_data[PALMAS_REG_SMPS7]->constraints.max_uV =
-									1380000;
-	}
+	/* Boot strapping 0, 2, 3 indicate Micron 1GB MT41K128M16-125
+	 * and it requires VDDIO_DDR 1.38V for stability.
+	 * Boot strapping 1 indicates Hynix 1GB H5TC2G63FFR-PBA and
+	 * it requires VDDIO_DDR 1.35V.
+	 */
+	tegranote7c_reg_data[PALMAS_REG_SMPS7]->constraints.min_uV =
+								1380000;
+	tegranote7c_reg_data[PALMAS_REG_SMPS7]->constraints.max_uV =
+								1380000;
 
-	if (board_info.board_id == BOARD_P1988 &&
-				board_info.fab >= BOARD_FAB_A01) {
-		palmas_pdata.clk32k_init_data = tegranote7c_palmas_clk32k_idata;
-		palmas_pdata.clk32k_init_data_size =
-				ARRAY_SIZE(tegranote7c_palmas_clk32k_idata);
-	}
+	palmas_pdata.clk32k_init_data = tegranote7c_palmas_clk32k_idata;
+	palmas_pdata.clk32k_init_data_size =
+			ARRAY_SIZE(tegranote7c_palmas_clk32k_idata);
 
 	if (get_androidboot_mode_charger())
 		palmas_pdata.long_press_delay =
@@ -791,22 +773,14 @@ static int __init tegranote7c_cl_dvfs_init(void)
 
 static int __init tegranote7c_fixed_regulator_init(void)
 {
-	struct board_info board_info;
 	int ret;
 
 	if (!machine_is_tegranote7c()) {
 		return 0;
 	}
 
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988)
-		ret = platform_add_devices(fixed_reg_devs_p1988,
-					   ARRAY_SIZE(fixed_reg_devs_p1988));
-	else
-		ret = platform_add_devices(fixed_reg_devs_e1569,
-					   ARRAY_SIZE(fixed_reg_devs_e1569));
-
+	ret = platform_add_devices(fixed_reg_devs_p1988,
+				   ARRAY_SIZE(fixed_reg_devs_p1988));
 	return ret;
 }
 subsys_initcall_sync(tegranote7c_fixed_regulator_init);
@@ -991,17 +965,6 @@ int __init tegranote7c_soctherm_init(void)
 
 	tegra_get_board_info(&board_info);
 
-	/*
-	 * P1988 has oc4 from ina230. E1569 has oc4 from pmic powergood
-	 * Disable oc4 throttle for E1569
-	 */
-	if (board_info.board_id == BOARD_E1569) {
-		tegranote7c_soctherm_data.throttle[THROTTLE_OC4]
-			.devs[THROTTLE_DEV_CPU].enable = false;
-		tegranote7c_soctherm_data.throttle[THROTTLE_OC4]
-			.devs[THROTTLE_DEV_GPU].enable = false;
-	}
-
 	tegra_platform_edp_init(tegranote7c_soctherm_data.therm[THERM_CPU].trips,
 			&tegranote7c_soctherm_data.therm[THERM_CPU].num_trips,
 			6000); /* edp temperature margin */
@@ -1010,14 +973,9 @@ int __init tegranote7c_soctherm_init(void)
 	tegra_add_vc_trips(tegranote7c_soctherm_data.therm[THERM_CPU].trips,
 			&tegranote7c_soctherm_data.therm[THERM_CPU].num_trips);
 
-	if (board_info.board_id != BOARD_E1569 &&
-			(board_info.board_id == BOARD_P1988 &&
-			(board_info.fab != BOARD_FAB_A00 &&
-			board_info.fab != BOARD_FAB_A01))) {
-		tegra_add_cdev_trips(
-			tegranote7c_soctherm_data.therm[THERM_CPU].trips,
-			&tegranote7c_soctherm_data.therm[THERM_CPU].num_trips);
-	}
+	tegra_add_cdev_trips(
+		tegranote7c_soctherm_data.therm[THERM_CPU].trips,
+		&tegranote7c_soctherm_data.therm[THERM_CPU].num_trips);
 
 	return tegra11_soctherm_init(&tegranote7c_soctherm_data);
 }
diff --git a/arch/arm/mach-tegra/board-tegranote7c-powermon.c b/arch/arm/mach-tegra/board-tegranote7c-powermon.c
index 9f907c17a539..18e85726fd74 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-powermon.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-powermon.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-tegranote7c-powermon.c
  *
- * Copyright (c) 2013, NVIDIA Corporation. All Rights Reserved.
+ * Copyright (c) 2014, NVIDIA Corporation. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -43,173 +43,6 @@ enum {
 	VA_AP_1V2,
 };
 
-static struct ina219_platform_data power_mon_ina219_info[] = {
-	[VD_CPU] = {
-		.calibration_data  = 0x7CD2,
-		.power_lsb = 2.563685298 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_CPU",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 1,
-	},
-
-	[VD_SOC] = {
-		.calibration_data  = 0x7CD2,
-		.power_lsb = 2.563685298 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_SOC",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 1,
-	},
-
-	[VS_DDR0] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VS_DDR0",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VS_DDR1] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VS_DDR1",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_LCD_HV] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_LCD_HV",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VS_SYS_1V8] = {
-		.calibration_data  = 0x7CD2,
-		.power_lsb = 2.563685298 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VS_SYS_1V8",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_AP_1V8] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_AP_1V8",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_AP_RTC] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_AP_RTC",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VS_AUD_SYS] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VS_AUD_SYS",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_DDR0] = {
-		.calibration_data  = 0xaec0,
-		.power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_DDR0",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_DDR1] = {
-		.calibration_data  = 0xaec0,
-		.power_lsb = 1.8311874106 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_DDR1",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VD_AP_VBUS] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VD_AP_VBUS",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 200,
-	},
-
-	[VS_SYS_2V9] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VS_SYS_2V9",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VA_PLLX] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VA_PLLX",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-
-	[VA_AP_1V2] = {
-		.calibration_data  = 0xfffe,
-		.power_lsb = 1.2500381481 * PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.rail_name = "VA_AP_1V2",
-		.divisor = 20,
-		.precision_multiplier = PRECISION_MULTIPLIER_TEGRANOTE7C,
-		.cont_conf = 0x3FFF,
-		.trig_conf = 0x1DB,
-		.shunt_resistor = 10,
-	},
-};
-
 enum {
 	INA_I2C_ADDR_40,
 	INA_I2C_ADDR_41,
@@ -228,98 +61,6 @@ enum {
 	INA_I2C_ADDR_4F,
 };
 
-static struct i2c_board_info tegranote7c_i2c1_ina219_board_info[] = {
-	[INA_I2C_ADDR_40] = {
-		I2C_BOARD_INFO("ina219", 0x40),
-		.platform_data = &power_mon_ina219_info[VD_CPU],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_41] = {
-		I2C_BOARD_INFO("ina219", 0x41),
-		.platform_data = &power_mon_ina219_info[VD_SOC],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_42] = {
-		I2C_BOARD_INFO("ina219", 0x42),
-		.platform_data = &power_mon_ina219_info[VS_DDR0],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_43] = {
-		I2C_BOARD_INFO("ina219", 0x43),
-		.platform_data = &power_mon_ina219_info[VS_DDR1],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_45] = {
-		I2C_BOARD_INFO("ina219", 0x45),
-		.platform_data = &power_mon_ina219_info[VD_LCD_HV],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_46] = {
-		I2C_BOARD_INFO("ina219", 0x46),
-		.platform_data = &power_mon_ina219_info[VS_SYS_1V8],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_47] = {
-		I2C_BOARD_INFO("ina219", 0x47),
-		.platform_data = &power_mon_ina219_info[VD_AP_1V8],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_48] = {
-		I2C_BOARD_INFO("ina219", 0x48),
-		.platform_data = &power_mon_ina219_info[VD_AP_RTC],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_49] = {
-		I2C_BOARD_INFO("ina219", 0x49),
-		.platform_data = &power_mon_ina219_info[VS_AUD_SYS],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4A] = {
-		I2C_BOARD_INFO("ina219", 0x4A),
-		.platform_data = &power_mon_ina219_info[VD_DDR0],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4B] = {
-		I2C_BOARD_INFO("ina219", 0x4B),
-		.platform_data = &power_mon_ina219_info[VD_DDR1],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4C] = {
-		I2C_BOARD_INFO("ina219", 0x4C),
-		.platform_data = &power_mon_ina219_info[VD_AP_VBUS],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4D] = {
-		I2C_BOARD_INFO("ina219", 0x4D),
-		.platform_data = &power_mon_ina219_info[VS_SYS_2V9],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4E] = {
-		I2C_BOARD_INFO("ina219", 0x4E),
-		.platform_data = &power_mon_ina219_info[VA_PLLX],
-		.irq = -1,
-	},
-
-	[INA_I2C_ADDR_4F] = {
-		I2C_BOARD_INFO("ina219", 0x4F),
-		.platform_data = &power_mon_ina219_info[VA_AP_1V2],
-		.irq = -1,
-	},
-};
-
 enum {
 	VDD_CELL
 };
@@ -355,16 +96,7 @@ static struct i2c_board_info tegranote7c_i2c1_ina230_board_info[] = {
 
 int __init tegranote7c_pmon_init(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	/* E1569 has ina219 for power measurement */
-	if (board_info.board_id == BOARD_E1569)
-		i2c_register_board_info(1, tegranote7c_i2c1_ina219_board_info,
-			ARRAY_SIZE(tegranote7c_i2c1_ina219_board_info));
-
-	/* Both E1569 and P1988 has ina230 for checking power at VDD_CELL */
+	/* P1988 has ina230 for checking power at VDD_CELL */
 	i2c_register_board_info(1, tegranote7c_i2c1_ina230_board_info,
 		ARRAY_SIZE(tegranote7c_i2c1_ina230_board_info));
 
diff --git a/arch/arm/mach-tegra/board-tegranote7c-sdhci.c b/arch/arm/mach-tegra/board-tegranote7c-sdhci.c
index a4c7e3ec1005..b4d0bbfeb6f5 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-sdhci.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-sdhci.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-tegranote7c-sdhci.c
  *
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -313,7 +313,6 @@ int __init tegranote7c_sdhci_init(void)
 	int nominal_core_mv;
 	int min_vcore_override_mv;
 	int boot_vcore_mv;
-	struct board_info board_info;
 	nominal_core_mv =
 		tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
 	if (nominal_core_mv) {
@@ -338,9 +337,7 @@ int __init tegranote7c_sdhci_init(void)
 		tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
 	}
 
-	tegra_get_board_info(&board_info);
-	if (board_info.board_id == BOARD_P1988)
-		tegra_sdhci_platform_data2.wp_gpio = -1;
+	tegra_sdhci_platform_data2.wp_gpio = -1;
 	if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200)
 	&& (!(tegra_sdhci_platform_data3.uhs_mask & MMC_UHS_MASK_DDR50)))
 		tegra_sdhci_platform_data3.trim_delay = 0;
diff --git a/arch/arm/mach-tegra/board-tegranote7c-sensors.c b/arch/arm/mach-tegra/board-tegranote7c-sensors.c
index 622b21f7d736..b130f3cc8a13 100644
--- a/arch/arm/mach-tegra/board-tegranote7c-sensors.c
+++ b/arch/arm/mach-tegra/board-tegranote7c-sensors.c
@@ -61,8 +61,6 @@
 #include "tegra-board-id.h"
 #include "dvfs.h"
 
-static struct board_info board_info;
-
 static struct throttle_table tj_throttle_table[] = {
 		/* CPU_THROT_LOW cannot be used by other than CPU */
 		/* NO_CAP cannot be used by CPU */
@@ -427,24 +425,6 @@ static int tegranote7c_camera_init(void)
 }
 
 /* MPU board file definition	*/
-static struct mpu_platform_data mpu6050_gyro_data_e1569 = {
-	.int_config	= 0x10,
-	.level_shifter	= 0,
-	/* Located in board_[platformname].h */
-	.orientation	= MPU_GYRO_ORIENTATION_E1569,
-	.key		= {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
-			   0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
-};
-
-static struct mpu_platform_data mpu6050_gyro_data_p1640_a01 = {
-	.int_config	= 0x10,
-	.level_shifter	= 0,
-	/* Located in board_[platformname].h */
-	.orientation	= MPU_GYRO_ORIENTATION_P1988_A01,
-	.key		= {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
-			   0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
-};
-
 static struct mpu_platform_data mpu6050_gyro_data = {
 	.int_config	= 0x10,
 	.level_shifter	= 0,
@@ -474,7 +454,6 @@ static void mpuirq_init(void)
 	unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
 	unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
 	char *gyro_name = MPU_GYRO_NAME;
-	struct board_info board_info;
 
 	pr_info("*** MPU START *** mpuirq_init...\n");
 
@@ -495,20 +474,11 @@ static void mpuirq_init(void)
 
 	inv_mpu6050_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
 
-	tegra_get_board_info(&board_info);
-	if (board_info.board_id == BOARD_E1569)
-		inv_mpu6050_i2c2_board_info[0].platform_data =
-			&mpu6050_gyro_data_e1569;
-	else if ((board_info.board_id == BOARD_P1988) &&
-			(board_info.fab <= BOARD_FAB_A01))
-		inv_mpu6050_i2c2_board_info[0].platform_data =
-			&mpu6050_gyro_data_p1640_a01;
-
 	i2c_register_board_info(gyro_bus_num, inv_mpu6050_i2c2_board_info,
 		ARRAY_SIZE(inv_mpu6050_i2c2_board_info));
 }
 
-static int tegranote7c_nct1008_init(void)
+static int __maybe_unused tegranote7c_nct1008_init(void)
 {
 	int nct1008_port;
 	int ret = 0;
@@ -555,29 +525,6 @@ static struct therm_est_subdevice skin_devs[] = {
 	{
 		.dev_data = "Tdiode",
 		.coeffs = {
-			3, 0, -2, -2,
-			-2, -2, -4, -2,
-			-2, -3, -4, -3,
-			-5, -2, -4, -3,
-			0, -3, -2, -22
-		},
-	},
-	{
-		.dev_data = "Tboard",
-		.coeffs = {
-			46, 11, 8, 10,
-			10, 12, 10, 13,
-			9, 8, 8, 9,
-			6, 6, 3, 5,
-			1, 3, -2, -27
-		},
-	},
-};
-
-static struct therm_est_subdevice skin_devs_a02[] = {
-	{
-		.dev_data = "Tdiode",
-		.coeffs = {
 			0, -1, -5, -6,
 			-6, -5, -5, -4,
 			-4, -4, -4, -4,
@@ -600,8 +547,11 @@ static struct therm_est_subdevice skin_devs_a02[] = {
 static struct therm_est_data skin_data = {
 	.num_trips = ARRAY_SIZE(skin_trips),
 	.trips = skin_trips,
+	.ndevs = ARRAY_SIZE(skin_devs),
+	.devs = skin_devs,
 	.polling_period = 1100,
 	.passive_delay = 15000,
+	.toffset = 799,
 	.tc1 = 10,
 	.tc2 = 1,
 };
@@ -643,22 +593,6 @@ static struct balanced_throttle skin_throttle = {
 static int __init tegranote7c_skin_init(void)
 {
 	if (machine_is_tegranote7c()) {
-		tegra_get_board_info(&board_info);
-		if (board_info.board_id == BOARD_E1569 ||
-			(board_info.board_id == BOARD_P1988 &&
-			(board_info.fab == BOARD_FAB_A00 ||
-			board_info.fab == BOARD_FAB_A01))) {
-			/* Use this for E1569 and P1988 A00/A01 */
-			skin_data.toffset = 5588;
-			skin_data.ndevs = ARRAY_SIZE(skin_devs);
-			skin_data.devs = skin_devs;
-		} else {
-			/* Use this after P1988 A02. */
-			skin_data.toffset = 799;
-			skin_data.ndevs = ARRAY_SIZE(skin_devs_a02);
-			skin_data.devs = skin_devs_a02;
-		}
-
 		balanced_throttle_register(&skin_throttle, "skin-balanced");
 		tegra_skin_therm_est_device.dev.platform_data = &skin_data;
 		platform_device_register(&tegra_skin_therm_est_device);
@@ -828,24 +762,11 @@ int __init tegranote7c_sensors_init(void)
 {
 	int err;
 
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_E1569 ||
-			(board_info.board_id == BOARD_P1988 &&
-			(board_info.fab == BOARD_FAB_A00 ||
-			board_info.fab == BOARD_FAB_A01))) {
-		err = tegranote7c_nct1008_init();
-		if (err) {
-			pr_err("%s: nct1008 register failed.\n", __func__);
-			return err;
-		}
-	} else {
-		err = platform_add_devices(gadc_thermal_devices,
-					   ARRAY_SIZE(gadc_thermal_devices));
-		if (err) {
-			pr_err("%s: gadc_thermal register failed\n", __func__);
-			return err;
-		}
+	err = platform_add_devices(gadc_thermal_devices,
+				   ARRAY_SIZE(gadc_thermal_devices));
+	if (err) {
+		pr_err("%s: gadc_thermal register failed\n", __func__);
+		return err;
 	}
 
 	tegratab_i2c1_ltr659ps_board_info[0].irq =
diff --git a/arch/arm/mach-tegra/board-tegranote7c.c b/arch/arm/mach-tegra/board-tegranote7c.c
index 31ef3c2d4972..6b43e2de4b64 100644
--- a/arch/arm/mach-tegra/board-tegranote7c.c
+++ b/arch/arm/mach-tegra/board-tegranote7c.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-tegranote7c.c
  *
- * Copyright (c) 2013 - 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -111,13 +111,8 @@ static struct platform_device btwilink_device = {
 
 static noinline void __init tegranote7c_bt_st(void)
 {
-	struct board_info board_info;
-
 	pr_info("tegranote7c_bt_st");
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988)
-		tegranote7c_wilink_pdata.nshutdown_gpio = TEGRA_GPIO_PR1;
+	tegranote7c_wilink_pdata.nshutdown_gpio = TEGRA_GPIO_PR1;
 
 	platform_device_register(&wl128x_device);
 	platform_device_register(&btwilink_device);
@@ -181,17 +176,6 @@ static __initdata struct tegra_clk_init_table tegranote7c_clk_init_table[] = {
 	{ NULL,		NULL,		0,		0},
 };
 
-static __initdata struct tegra_clk_init_table e1569_wifi_clk_init_table[] = {
-	{ "blink",	"clk_32k",	32768,		true},
-	{ NULL,		NULL,		0,		0},
-};
-
-static __initdata struct tegra_clk_init_table P1988_wifi_clk_init_table[] = {
-	{ "extern3",	"clk_32k",	32768,		true},
-	{ "clk_out_3",	"extern3",	32768,		true},
-	{ NULL,		NULL,		0,		0},
-};
-
 #ifdef CONFIG_USE_OF
 static struct tegra_i2c_platform_data tegranote7c_i2c1_platform_data = {
 	.adapter_nr	= 0,
@@ -240,24 +224,13 @@ static struct tegra_i2c_platform_data tegranote7c_i2c5_platform_data = {
 };
 #endif
 
-static struct i2c_board_info __initdata rt5640_board_info = {
-	I2C_BOARD_INFO("rt5640", 0x1c),
-};
-
 static struct i2c_board_info __initdata rt5639_board_info = {
 	I2C_BOARD_INFO("rt5639", 0x1c),
 };
 
 static void tegranote7c_i2c_init(void)
 {
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988)
-		i2c_register_board_info(0, &rt5639_board_info, 1);
-	else
-		i2c_register_board_info(0, &rt5640_board_info, 1);
+	i2c_register_board_info(0, &rt5639_board_info, 1);
 }
 
 static struct platform_device *tegranote7c_uart_devices[] __initdata = {
@@ -361,6 +334,10 @@ static struct platform_device tegranote7c_tegra_wakeup_monitor_device = {
 #endif
 
 static struct tegra_asoc_platform_data tegranote7c_audio_pdata = {
+	.codec_name = "rt5639.0-001c",
+	.codec_dai_name = "rt5639-aif1",
+	.gpio_hp_det = TEGRA_GPIO_CDC_IRQ,
+	.use_codec_jd_irq = true,
 	.gpio_spkr_en		= TEGRA_GPIO_SPKR_EN,
 	.gpio_hp_mute		= -1,
 	.gpio_int_mic_en	= TEGRA_GPIO_INT_MIC_EN,
@@ -609,29 +586,6 @@ static void tegranote7c_usb_init(void) { }
 static void tegranote7c_modem_init(void) { }
 #endif
 
-static void tegranote7c_audio_init(void)
-{
-	struct board_info board_info;
-
-	tegra_get_board_info(&board_info);
-
-	if (board_info.board_id == BOARD_P1988) {
-		tegranote7c_audio_pdata.codec_name = "rt5639.0-001c";
-		tegranote7c_audio_pdata.codec_dai_name = "rt5639-aif1";
-		if (board_info.fab == BOARD_FAB_A00)
-			tegranote7c_audio_pdata.gpio_hp_det = TEGRA_GPIO_HP_DET;
-		else {/* from A01, CDC_IRQ from codec is used as interrupt */
-			tegranote7c_audio_pdata.gpio_hp_det = TEGRA_GPIO_CDC_IRQ;
-			tegranote7c_audio_pdata.use_codec_jd_irq = true;
-		}
-	} else {
-		tegranote7c_audio_pdata.codec_name = "rt5640.0-001c";
-		tegranote7c_audio_pdata.codec_dai_name = "rt5640-aif1";
-		tegranote7c_audio_pdata.gpio_hp_det = TEGRA_GPIO_HP_DET;
-	}
-}
-
-
 static struct platform_device *tegranote7c_spi_devices[] __initdata = {
 	&tegra11_spi_device1,
 };
@@ -748,17 +702,12 @@ struct spi_board_info rm31080a_tegranote7c_spi_board[1] = {
 
 static int __init tegranote7c_touch_init(void)
 {
-	struct board_info board_info;
-
 	if (get_androidboot_mode_charger())
 		return 0;
 
-	tegra_get_board_info(&board_info);
-
 #if defined(CONFIG_TOUCHSCREEN_MAXIM_STI) || \
 	defined(CONFIG_TOUCHSCREEN_MAXIM_STI_MODULE)
-	if (board_info.board_id == BOARD_P1988)
-		(void)touch_init_maxim_sti(&maxim_sti_spi_board);
+	(void)touch_init_maxim_sti(&maxim_sti_spi_board);
 #else
 	tegra_clk_init_from_table(touch_clk_init_table);
 	rm31080ts_tegranote7c_data.platform_id = RM_PLATFORM_D010;
@@ -776,16 +725,7 @@ static int __init tegranote7c_touch_init(void)
 
 static void __init tegra_tegranote7c_early_init(void)
 {
-	struct board_info board_info;
-
 	tegra_clk_init_from_table(tegranote7c_clk_init_table);
-	/* enable wifi 32K clk according to board revision */
-	tegra_get_board_info(&board_info);
-	if (board_info.board_id == BOARD_E1569)
-		tegra_clk_init_from_table(e1569_wifi_clk_init_table);
-	else if (board_info.board_id == BOARD_P1988 &&
-			board_info.fab == BOARD_FAB_A00)
-		tegra_clk_init_from_table(P1988_wifi_clk_init_table);
 	tegra_clk_verify_parents();
 	tegra_soc_device_init("tegranote7c");
 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
@@ -887,7 +827,6 @@ static void __init tegra_tegranote7c_late_init(void)
 	tegranote7c_spi_init();
 	tegranote7c_usb_init();
 	tegranote7c_uart_init();
-	tegranote7c_audio_init();
 	platform_add_devices(tegranote7c_devices, ARRAY_SIZE(tegranote7c_devices));
 	tegra_ram_console_debug_init();
 	tegra_io_dpd_init();
diff --git a/arch/arm/mach-tegra/board-tegranote7c.h b/arch/arm/mach-tegra/board-tegranote7c.h
index 2218615fb13c..ceb5b8e6dd2c 100644
--- a/arch/arm/mach-tegra/board-tegranote7c.h
+++ b/arch/arm/mach-tegra/board-tegranote7c.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-tegranote7c.h
  *
- * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -85,14 +85,11 @@
 #define MPU_GYRO_IRQ_GPIO             TEGRA_GPIO_PR3
 #define MPU_GYRO_ADDR                 0x69
 #define MPU_GYRO_BUS_NUM              0
-#define MPU_GYRO_ORIENTATION_E1569    MTMAT_TOP_CCW_180
-#define MPU_GYRO_ORIENTATION_P1988_A01 MTMAT_TOP_CCW_0
 #define MPU_GYRO_ORIENTATION          MTMAT_TOP_CCW_90
 #define MPU_COMPASS_NAME              "ak8975"
 #define MPU_COMPASS_IRQ_GPIO          0
 #define MPU_COMPASS_ADDR              0x0D
 #define MPU_COMPASS_BUS_NUM           0
-#define MPU_COMPASS_ORIENTATION_E1569 MTMAT_TOP_CCW_180
 #define MPU_COMPASS_ORIENTATION       MTMAT_BOT_CCW_270
 
 /* Modem related GPIOs */
diff --git a/arch/arm/mach-tegra/tegra11_emc.c b/arch/arm/mach-tegra/tegra11_emc.c
index c2498bd99719..bd623f5c0336 100644
--- a/arch/arm/mach-tegra/tegra11_emc.c
+++ b/arch/arm/mach-tegra/tegra11_emc.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra11_emc.c
  *
- * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -1153,10 +1153,6 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
 				/* force select ram strapping 0x0 */
 				if (reg == 0x0)
 					return of_node_get(iter);
-			} else if (board_info.board_id == BOARD_P1988 &&
-				board_info.fab >= BOARD_FAB_A04) {
-				if (reg == tegra_bct_strapping)
-					return of_node_get(iter);
 			} else if (board_info.board_id == BOARD_P1988) {
 				/* force select ram strapping 0x0 */
 				if (reg == 0x0)