diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2011-05-11 15:28:18 +0300 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-15 16:50:03 -0700 |
| commit | 844983ef04e9521595451829757fdcdc020273b2 (patch) | |
| tree | ae9577ce804e4d31332871b75f97e23b00fc2336 /arch | |
| parent | 8494a39c23c38945171b153546c6d7db05fb78b6 (diff) | |
ARM: tegra: power: save and restore perfmon context
Change-Id: Ibc863b2af70371810305df195a5f4e37cd4f01f5
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31159
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/cortex-a9.S | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S index abe2b4a1b474..6a9d318b5fe9 100644 --- a/arch/arm/mach-tegra/cortex-a9.S +++ b/arch/arm/mach-tegra/cortex-a9.S @@ -126,6 +126,14 @@ #define CTS_CP14_WPT_2 592 #define CTS_CP14_WPT_3 600 +/* + * perfmon unit context : + * 2 32-bit control registers + * 1 32-bit cycle counter + * for each counter 1 32-bit event select register and 1 32-bit value +*/ +#define CTX_PERFMON 700 + #include "power.h" #include "power-macros.S" @@ -367,6 +375,26 @@ ENTRY(__cortex_a9_save) mrc p14, 0, r3, c0, c3, 7 stmia r9!, {r2-r3} @ WPT_0 + /* save CP15 perfmon context */ + add r9, r8, #CTX_PERFMON + mrc p15, 0, r2, c9, c12, 0 @ PMCR + bic r0, r2, #1 @ disable counters + mcr p15, 0, r0, c9, c12, 0 + mrc p15, 0, r3, c9, c12, 1 @ PMCNTENSET + mrc p15, 0, r4, c9, c13, 0 @ PMCCNTR + stmia r9!, {r2-r4} + mov r0, r0, LSR #11 + and r0, r0, #0x3f + sub r0, r0, #1 +1: + mcr p15, 0, r0, c9, c12, 5 @ PMSELR + mrc p15, 0, r4, c9, c13, 1 @ PMXEVTYPER + mrc p15, 0, r5, c9, c13, 2 @ PMXEVCNTR + stmia r9!, {r4-r5} + subs r0, r0, #1 + bpl 1b + + #ifdef CONFIG_CACHE_L2X0 cpu_id r4 cmp r4, #0 @@ -540,6 +568,24 @@ ENTRY(__cortex_a9_restore) mcr p14, 0, r0, c0, c2, 2 @ DSCR isb + /* restore CP15 perfmon context */ + add r9, r8, #CTX_PERFMON + ldmia r9!, {r2-r4} + mcr p15, 0, r4, c9, c13, 0 @ PMCCNTR + mov r0, r2, LSR #11 + and r0, r0, #0x3f + sub r0, r0, #1 +1: + ldmia r9!, {r4-r5} + mcr p15, 0, r0, c9, c12, 5 @ PMSELR + mcr p15, 0, r4, c9, c13, 1 @ PMXEVTYPER + mcr p15, 0, r5, c9, c13, 2 @ PMXEVCNTR + subs r0, r0, #1 + bpl 1b + + mcr p15, 0, r3, c9, c12, 1 @ PMCNTENSET + mcr p15, 0, r2, c9, c12, 0 @ PMCR + #ifdef CONFIG_VFPv3 orr r4, lr, #0xF00000 mcr p15, 0, r4, c1, c0, 2 @ enable coproc access |