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| author | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:02 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-03-10 10:25:02 +0000 |
| commit | 4930f75897bf89f8aa9e9e99dec2412bf3624d37 (patch) | |
| tree | 53f91d0af673fb1f494d073547041a12be30e46f /arch | |
| parent | 55b501dc23d3e39ff5d5c74b7b3920f5f0d9343a (diff) | |
Stale prediction on replaced interworking branch on Cortex-A8
This patch adds the workaround for the 430973 Cortex-A8 (r1p0)
erratum. The BTAC/BTB is now flushed at every context switch.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 14 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 8 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4b7b257a1463..eb750514c699 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -695,6 +695,20 @@ config ARM_ERRATA_351422 situation. This option adds variable spinning time to the locking routines. +config ARM_ERRATA_430973 + bool "Stale prediction on replaced interworking branch on Cortex-A8" + depends on CPU_V7 + default n + help + This option enables the workaround for the 430973 Cortex-A8 + (r1p0) erratum. If a code sequence containing an ARM/Thumb + interworking branch is replaced with another code sequence + at the same virtual address, whether due to self-modifying + code or virtual to physical address re-mapping, Cortex-A8 + does not recover from the stale interworking branch + prediction. This results in Cortex-A8 executing the new code + sequence in the incorrect ARM or Thumb state. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 41615a3c11ae..2848d0588e68 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -98,6 +98,9 @@ ENTRY(cpu_v7_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id orr r0, r0, #TTB_FLAGS +#ifdef CONFIG_ARM_ERRATA_430973 + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB +#endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -192,6 +195,11 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} +#ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 6) @ set IBE to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |