ENGR00125323-3: MX53: Change MXC iomux to use iomux-v3

Change mx53 EVK and Armadillo2 iomux to use iomux-v3.

- Creates iomux-mx53.h to defines IOMUX pins for MX53 HW
- Moves pin structure and functions that were in
  mx53_evk_gpio.c into mx53_evk.c and delete
  mx53_evk_gpio.c.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>

7 files changed, 1251 insertions, 1780 deletions

diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 72733a6dddfa..458c46f57510 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -14,5 +14,5 @@ obj-$(CONFIG_ARCH_MX50) += clock_mx50.o mx50_suspend.o
 
 obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o
+obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o
diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c
index 443857c76a84..4e0df2d6baf2 100644
--- a/arch/arm/mach-mx5/mx53_evk.c
+++ b/arch/arm/mach-mx5/mx53_evk.c
@@ -57,12 +57,46 @@
 #include <mach/gpio.h>
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
-#include "iomux.h"
-#include "mx53_pins.h"
+#include <mach/iomux-mx53.h>
+
 #include "crm_regs.h"
 #include "devices.h"
 #include "usb.h"
 
+#define ARM2_SD1_CD			(0*32 + 1)	/* GPIO_1_1 */
+
+#define MX53_HP_DETECT			(1*32 + 5)	/* GPIO_2_5 */
+
+#define EVK_SD3_CD			(2*32 + 11)	/* GPIO_3_11 */
+#define EVK_SD3_WP			(2*32 + 12)	/* GPIO_3_12 */
+#define EVK_SD1_CD			(2*32 + 13)	/* GPIO_3_13 */
+#define EVK_SD1_WP			(2*32 + 14)	/* GPIO_3_14 */
+#define ARM2_OTG_VBUS			(2*32 + 22)	/* GPIO_3_22 */
+#define MX53_DVI_PD			(2*32 + 24)	/* GPIO_3_24 */
+#define EVK_TS_INT			(2*32 + 26)	/* GPIO_3_26 */
+#define MX53_DVI_I2C			(2*32 + 28)	/* GPIO_3_28 */
+#define MX53_DVI_DETECT		(2*32 + 31)	/* GPIO_3_31 */
+
+#define MX53_CAM_RESET			(3*32 + 0)	/* GPIO_4_0 */
+#define MX53_ESAI_RESET			(3*32 + 2)	/* GPIO_4_2 */
+#define MX53_CAN2_EN2			(3*32 + 4)	/* GPIO_4_4 */
+#define MX53_12V_EN			(3*32 + 5)	/* GPIO_4_5 */
+#define ARM2_LCD_CONTRAST		(3*32 + 20)	/* GPIO_4_20 */
+
+#define MX53_DVI_RESET			(4*32 + 0)	/* GPIO_5_0 */
+#define EVK_USB_HUB_RESET		(4*32 + 20)	/* GPIO_5_20 */
+#define MX53_TVIN_PWR			(4*32 + 23)	/* GPIO_5_23 */
+#define MX53_CAN2_EN1			(4*32 + 24)	/* GPIO_5_24 */
+#define MX53_TVIN_RESET			(4*32 + 25)	/* GPIO_5_25 */
+
+#define EVK_OTG_VBUS			(5*32 + 6)	/* GPIO_6_6 */
+
+#define EVK_FEC_PHY_RESET		(6*32 + 6)	/* GPIO_7_6 */
+#define EVK_USBH1_VBUS			(6*32 + 8)	/* GPIO_7_8 */
+#define MX53_PMIC_INT			(6*32 + 11)	/* GPIO_7_11 */
+#define MX53_CAN1_EN1			(6*32 + 12)	/* GPIO_7_12 */
+#define MX53_CAN1_EN2			(6*32 + 13)	/* GPIO_7_13 */
+
 /*!
  * @file mach-mx53/mx53_evk.c
  *
@@ -71,11 +105,297 @@
  * @ingroup MSL_MX53
  */
 extern int __init mx53_evk_init_mc13892(void);
-extern void __init mx53_evk_io_init(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
 static int num_cpu_wp = 3;
 
+static struct pad_desc mx53common_pads[] = {
+	MX53_PAD_EIM_WAIT__GPIO_5_0,
+
+	MX53_PAD_EIM_OE__DI1_PIN7,
+	MX53_PAD_EIM_RW__DI1_PIN8,
+
+	MX53_PAD_EIM_A25__DI0_D1_CS,
+
+	MX53_PAD_EIM_D16__CSPI1_SCLK,
+	MX53_PAD_EIM_D17__CSPI1_MISO,
+	MX53_PAD_EIM_D18__CSPI1_MOSI,
+
+	MX53_PAD_EIM_D20__SER_DISP0_CS,
+
+	MX53_PAD_EIM_D23__DI0_D0_CS,
+
+	MX53_PAD_EIM_D24__GPIO_3_24,
+	MX53_PAD_EIM_D26__GPIO_3_26,
+
+	MX53_PAD_EIM_D29__DISPB0_SER_RS,
+
+	MX53_PAD_EIM_D30__DI0_PIN11,
+	MX53_PAD_EIM_D31__DI0_PIN12,
+
+	MX53_PAD_ATA_DA_1__GPIO_7_7,
+	MX53_PAD_ATA_DATA4__GPIO_2_4,
+	MX53_PAD_ATA_DATA5__GPIO_2_5,
+	MX53_PAD_ATA_DATA6__GPIO_2_6,
+
+	MX53_PAD_SD2_CLK__SD2_CLK,
+	MX53_PAD_SD2_CMD__SD2_CMD,
+	MX53_PAD_SD2_DATA0__SD2_DAT0,
+	MX53_PAD_SD2_DATA1__SD2_DAT1,
+	MX53_PAD_SD2_DATA2__SD2_DAT2,
+	MX53_PAD_SD2_DATA3__SD2_DAT3,
+	MX53_PAD_ATA_DATA12__SD2_DAT4,
+	MX53_PAD_ATA_DATA13__SD2_DAT5,
+	MX53_PAD_ATA_DATA14__SD2_DAT6,
+	MX53_PAD_ATA_DATA15__SD2_DAT7,
+
+	MX53_PAD_CSI0_D10__UART1_TXD,
+	MX53_PAD_CSI0_D11__UART1_RXD,
+
+	MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+	MX53_PAD_ATA_DMARQ__UART2_TXD,
+	MX53_PAD_ATA_DIOR__UART2_RTS,
+	MX53_PAD_ATA_INTRQ__UART2_CTS,
+
+	MX53_PAD_ATA_CS_0__UART3_TXD,
+	MX53_PAD_ATA_CS_1__UART3_RXD,
+
+	MX53_PAD_KEY_COL0__AUD5_TXC,
+	MX53_PAD_KEY_ROW0__AUD5_TXD,
+	MX53_PAD_KEY_COL1__AUD5_TXFS,
+	MX53_PAD_KEY_ROW1__AUD5_RXD,
+
+	MX53_PAD_CSI0_D7__GPIO_5_25,
+
+	MX53_PAD_GPIO_2__MLBDAT,
+	MX53_PAD_GPIO_3__MLBCLK,
+
+	MX53_PAD_GPIO_6__MLBSIG,
+
+	MX53_PAD_GPIO_4__GPIO_1_4,
+	MX53_PAD_GPIO_7__GPIO_1_7,
+	MX53_PAD_GPIO_8__GPIO_1_8,
+
+	MX53_PAD_GPIO_10__GPIO_4_0,
+
+	MX53_PAD_KEY_COL2__TXCAN1,
+	MX53_PAD_KEY_ROW2__RXCAN1,
+
+	/* CAN1 -- EN */
+	MX53_PAD_GPIO_18__GPIO_7_13,
+	/* CAN1 -- STBY */
+	MX53_PAD_GPIO_17__GPIO_7_12,
+	/* CAN1 -- NERR */
+	MX53_PAD_GPIO_5__GPIO_1_5,
+
+	MX53_PAD_KEY_COL4__TXCAN2,
+	MX53_PAD_KEY_ROW4__RXCAN2,
+
+	/* CAN2 -- EN */
+	MX53_PAD_CSI0_D6__GPIO_5_24,
+	/* CAN2 -- STBY */
+	MX53_PAD_GPIO_14__GPIO_4_4,
+	/* CAN2 -- NERR */
+	MX53_PAD_CSI0_D4__GPIO_5_22,
+
+	MX53_PAD_GPIO_11__GPIO_4_1,
+	MX53_PAD_GPIO_12__GPIO_4_2,
+	MX53_PAD_GPIO_13__GPIO_4_3,
+	MX53_PAD_GPIO_16__GPIO_7_11,
+	MX53_PAD_GPIO_19__GPIO_4_5,
+
+	/* DI0 display clock */
+	MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK,
+
+	/* DI0 data enable */
+	MX53_PAD_DI0_PIN15__DI0_PIN15,
+	/* DI0 HSYNC */
+	MX53_PAD_DI0_PIN2__DI0_PIN2,
+	/* DI0 VSYNC */
+	MX53_PAD_DI0_PIN3__DI0_PIN3,
+
+	MX53_PAD_DISP0_DAT0__DISP0_DAT0,
+	MX53_PAD_DISP0_DAT1__DISP0_DAT1,
+	MX53_PAD_DISP0_DAT2__DISP0_DAT2,
+	MX53_PAD_DISP0_DAT3__DISP0_DAT3,
+	MX53_PAD_DISP0_DAT4__DISP0_DAT4,
+	MX53_PAD_DISP0_DAT5__DISP0_DAT5,
+	MX53_PAD_DISP0_DAT6__DISP0_DAT6,
+	MX53_PAD_DISP0_DAT7__DISP0_DAT7,
+	MX53_PAD_DISP0_DAT8__DISP0_DAT8,
+	MX53_PAD_DISP0_DAT9__DISP0_DAT9,
+	MX53_PAD_DISP0_DAT10__DISP0_DAT10,
+	MX53_PAD_DISP0_DAT11__DISP0_DAT11,
+	MX53_PAD_DISP0_DAT12__DISP0_DAT12,
+	MX53_PAD_DISP0_DAT13__DISP0_DAT13,
+	MX53_PAD_DISP0_DAT14__DISP0_DAT14,
+	MX53_PAD_DISP0_DAT15__DISP0_DAT15,
+	MX53_PAD_DISP0_DAT16__DISP0_DAT16,
+	MX53_PAD_DISP0_DAT17__DISP0_DAT17,
+	MX53_PAD_DISP0_DAT18__DISP0_DAT18,
+	MX53_PAD_DISP0_DAT19__DISP0_DAT19,
+	MX53_PAD_DISP0_DAT20__DISP0_DAT20,
+	MX53_PAD_DISP0_DAT21__DISP0_DAT21,
+	MX53_PAD_DISP0_DAT22__DISP0_DAT22,
+	MX53_PAD_DISP0_DAT23__DISP0_DAT23,
+
+	MX53_PAD_LVDS0_TX3_P__LVDS0_TX3,
+	MX53_PAD_LVDS0_CLK_P__LVDS0_CLK,
+	MX53_PAD_LVDS0_TX2_P__LVDS0_TX2,
+	MX53_PAD_LVDS0_TX1_P__LVDS0_TX1,
+	MX53_PAD_LVDS0_TX0_P__LVDS0_TX0,
+
+	MX53_PAD_LVDS1_TX3_P__LVDS1_TX3,
+	MX53_PAD_LVDS1_CLK_P__LVDS1_CLK,
+	MX53_PAD_LVDS1_TX2_P__LVDS1_TX2,
+	MX53_PAD_LVDS1_TX1_P__LVDS1_TX1,
+	MX53_PAD_LVDS1_TX0_P__LVDS1_TX0,
+
+	/* audio and CSI clock out */
+	MX53_PAD_GPIO_0__SSI_EXT1_CLK,
+
+	MX53_PAD_CSI0_D12__CSI0_D12,
+	MX53_PAD_CSI0_D13__CSI0_D13,
+	MX53_PAD_CSI0_D14__CSI0_D14,
+	MX53_PAD_CSI0_D15__CSI0_D15,
+	MX53_PAD_CSI0_D16__CSI0_D16,
+	MX53_PAD_CSI0_D17__CSI0_D17,
+	MX53_PAD_CSI0_D18__CSI0_D18,
+	MX53_PAD_CSI0_D19__CSI0_D19,
+
+	MX53_PAD_CSI0_VSYNC__CSI0_VSYNC,
+	MX53_PAD_CSI0_MCLK__CSI0_HSYNC,
+	MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK,
+	/* Camera low power */
+	MX53_PAD_CSI0_D5__GPIO_5_23,
+
+	/* esdhc1 */
+	MX53_PAD_SD1_CMD__SD1_CMD,
+	MX53_PAD_SD1_CLK__SD1_CLK,
+	MX53_PAD_SD1_DATA0__SD1_DATA0,
+	MX53_PAD_SD1_DATA1__SD1_DATA1,
+	MX53_PAD_SD1_DATA2__SD1_DATA2,
+	MX53_PAD_SD1_DATA3__SD1_DATA3,
+
+	/* esdhc3 */
+	MX53_PAD_ATA_DATA8__SD3_DAT0,
+	MX53_PAD_ATA_DATA9__SD3_DAT1,
+	MX53_PAD_ATA_DATA10__SD3_DAT2,
+	MX53_PAD_ATA_DATA11__SD3_DAT3,
+	MX53_PAD_ATA_DATA0__SD3_DAT4,
+	MX53_PAD_ATA_DATA1__SD3_DAT5,
+	MX53_PAD_ATA_DATA2__SD3_DAT6,
+	MX53_PAD_ATA_DATA3__SD3_DAT7,
+	MX53_PAD_ATA_RESET_B__SD3_CMD,
+	MX53_PAD_ATA_IORDY__SD3_CLK,
+
+	/* FEC pins */
+	MX53_PAD_FEC_MDIO__FEC_MDIO,
+	MX53_PAD_FEC_REF_CLK__FEC_REF_CLK,
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+	MX53_PAD_FEC_CRS_DV__FEC_CRS_DV,
+	MX53_PAD_FEC_RXD1__FEC_RXD1,
+	MX53_PAD_FEC_RXD0__FEC_RXD0,
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX53_PAD_FEC_TXD1__FEC_TXD1,
+	MX53_PAD_FEC_TXD0__FEC_TXD0,
+	MX53_PAD_FEC_MDC__FEC_MDC,
+
+	MX53_PAD_CSI0_D8__I2C1_SDA,
+	MX53_PAD_CSI0_D9__I2C1_SCL,
+
+	MX53_PAD_KEY_COL3__I2C2_SCL,
+	MX53_PAD_KEY_ROW3__I2C2_SDA,
+};
+
+static struct pad_desc mx53evk_pads[] = {
+	/* USB OTG USB_OC */
+	MX53_PAD_EIM_A24__GPIO_5_4,
+
+	/* USB OTG USB_PWR */
+	MX53_PAD_EIM_A23__GPIO_6_6,
+
+	/* DISPB0_SER_CLK */
+	MX53_PAD_EIM_D21__DISPB0_SER_CLK,
+
+	/* DI0_PIN1 */
+	MX53_PAD_EIM_D22__DISPB0_SER_DIN,
+
+	/* DVI I2C ENABLE */
+	MX53_PAD_EIM_D28__GPIO_3_28,
+
+	/* DVI DET */
+	MX53_PAD_EIM_D31__GPIO_3_31,
+
+	/* SDHC1 SD_CD */
+	MX53_PAD_EIM_DA13__GPIO_3_13,
+
+	/* SDHC1 SD_WP */
+	MX53_PAD_EIM_DA14__GPIO_3_14,
+
+	/* SDHC3 SD_CD */
+	MX53_PAD_EIM_DA11__GPIO_3_11,
+
+	/* SDHC3 SD_WP */
+	MX53_PAD_EIM_DA12__GPIO_3_12,
+
+	/* PWM backlight */
+	MX53_PAD_GPIO_1__PWMO,
+
+	/* USB HOST USB_PWR */
+	MX53_PAD_ATA_DA_2__GPIO_7_8,
+
+	/* USB HOST USB_RST */
+	MX53_PAD_CSI0_DATA_EN__GPIO_5_20,
+
+	/* USB HOST CARD_ON */
+	MX53_PAD_EIM_DA15__GPIO_3_15,
+
+	/* USB HOST CARD_RST */
+	MX53_PAD_ATA_DATA7__GPIO_2_7,
+
+	/* USB HOST WAN_WAKE */
+	MX53_PAD_EIM_D25__GPIO_3_25,
+
+	/* FEC_RST */
+	MX53_PAD_ATA_DA_0__GPIO_7_6,
+};
+
+static struct pad_desc mx53arm2_pads[] = {
+	/* USB OTG USB_OC */
+	MX53_PAD_EIM_D21__GPIO_3_21,
+
+	/* USB OTG USB_PWR */
+	MX53_PAD_EIM_D22__GPIO_3_22,
+
+	/* SDHC1 SD_CD */
+	MX53_PAD_GPIO_1__GPIO_1_1,
+
+	/* gpio backlight */
+	MX53_PAD_DI0_PIN4__GPIO_4_20,
+};
+
+static struct pad_desc mx53_nand_pads[] = {
+	MX53_PAD_NANDF_CLE__NANDF_CLE,
+	MX53_PAD_NANDF_ALE__NANDF_ALE,
+	MX53_PAD_NANDF_WP_B__NANDF_WP_B,
+	MX53_PAD_NANDF_WE_B__NANDF_WE_B,
+	MX53_PAD_NANDF_RE_B__NANDF_RE_B,
+	MX53_PAD_NANDF_RB0__NANDF_RB0,
+	MX53_PAD_NANDF_CS0__NANDF_CS0,
+	MX53_PAD_NANDF_CS1__NANDF_CS1	,
+	MX53_PAD_NANDF_CS2__NANDF_CS2,
+	MX53_PAD_NANDF_CS3__NANDF_CS3	,
+	MX53_PAD_EIM_DA0__EIM_DA0,
+	MX53_PAD_EIM_DA1__EIM_DA1,
+	MX53_PAD_EIM_DA2__EIM_DA2,
+	MX53_PAD_EIM_DA3__EIM_DA3,
+	MX53_PAD_EIM_DA4__EIM_DA4,
+	MX53_PAD_EIM_DA5__EIM_DA5,
+	MX53_PAD_EIM_DA6__EIM_DA6,
+	MX53_PAD_EIM_DA7__EIM_DA7,
+};
+
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -192,7 +512,37 @@ static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
 	.pwm_period_ns = 78770,
 };
 
-extern void flexcan_xcvr_enable(int id, int en);
+static void flexcan_xcvr_enable(int id, int en)
+{
+	static int pwdn;
+	if (id < 0 || id > 1)
+		return;
+
+	if (en) {
+		if (!(pwdn++))
+			gpio_set_value(MX53_12V_EN, 1);
+
+		if (id == 0) {
+			gpio_set_value(MX53_CAN1_EN1, 1);
+			gpio_set_value(MX53_CAN1_EN2, 1);
+		} else {
+			gpio_set_value(MX53_CAN2_EN1, 1);
+			gpio_set_value(MX53_CAN2_EN2, 1);
+		}
+
+	} else {
+		if (!(--pwdn))
+			gpio_set_value(MX53_12V_EN, 0);
+
+		if (id == 0) {
+			gpio_set_value(MX53_CAN1_EN1, 0);
+			gpio_set_value(MX53_CAN1_EN2, 0);
+		} else {
+			gpio_set_value(MX53_CAN2_EN1, 0);
+			gpio_set_value(MX53_CAN2_EN2, 0);
+		}
+	}
+}
 
 static struct flexcan_platform_data flexcan0_data = {
 	.core_reg = NULL,
@@ -244,10 +594,69 @@ static struct fec_platform_data fec_data = {
 	.phy = PHY_INTERFACE_MODE_RMII,
 };
 
-extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
-						    int chipselect);
-extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-						      int chipselect);
+/* workaround for ecspi chipselect pin may not keep correct level when idle */
+static void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
+					     int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		switch (chipselect) {
+		case 0x1:
+			{
+			struct pad_desc eim_d19_gpio = MX53_PAD_EIM_D19__GPIO_3_19;
+			struct pad_desc cspi_ss0 = MX53_PAD_EIM_EB2__CSPI_SS0;
+
+			/* de-select SS1 of instance: ecspi1. */
+			mxc_iomux_v3_setup_pad(&eim_d19_gpio);
+			mxc_iomux_v3_setup_pad(&cspi_ss0);
+			}
+			break;
+		case 0x2:
+			{
+			struct pad_desc eim_eb2_gpio = MX53_PAD_EIM_EB2__GPIO_2_30;
+			struct pad_desc cspi_ss1 = MX53_PAD_EIM_D19__CSPI_SS1;
+
+			/* de-select SS0 of instance: ecspi1. */
+			mxc_iomux_v3_setup_pad(&eim_eb2_gpio);
+			mxc_iomux_v3_setup_pad(&cspi_ss1);
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+	case 2:
+		break;
+	case 3:
+		break;
+	default:
+		break;
+	}
+}
+
+static void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+					       int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		switch (chipselect) {
+		case 0x1:
+			break;
+		case 0x2:
+			break;
+		default:
+			break;
+		}
+		break;
+	case 2:
+		break;
+	case 3:
+		break;
+	default:
+		break;
+	}
+}
+
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
@@ -297,18 +706,98 @@ static struct ldb_platform_data ldb_data = {
 	.ext_ref = 1,
 };
 
+static struct pad_desc mx53esai_pads[] = {
+	MX53_PAD_FEC_MDIO__ESAI_SCKR,
+	MX53_PAD_FEC_REF_CLK__ESAI_FSR,
+	MX53_PAD_FEC_RX_ER__ESAI_HCKR,
+	MX53_PAD_FEC_CRS_DV__ESAI_SCKT,
+	MX53_PAD_FEC_RXD1__ESAI_FST,
+	MX53_PAD_FEC_RXD0__ESAI_HCKT,
+	MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2,
+	MX53_PAD_FEC_TXD1__ESAI_TX2_RX3,
+	MX53_PAD_FEC_TXD0__ESAI_TX4_RX1,
+	MX53_PAD_FEC_MDC__ESAI_TX5_RX0,
+	MX53_PAD_NANDF_CS2__ESAI_TX0,
+	MX53_PAD_NANDF_CS3__ESAI_TX1,
+};
+
+void gpio_activate_esai_ports(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx53esai_pads,
+					ARRAY_SIZE(mx53esai_pads));
+}
+
 static struct mxc_esai_platform_data esai_data = {
 	.activate_esai_ports = gpio_activate_esai_ports,
 };
 
+void gpio_cs42888_pdwn(int pdwn)
+{
+	if (pdwn)
+		gpio_set_value(MX53_ESAI_RESET, 0);
+	else
+		gpio_set_value(MX53_ESAI_RESET, 1);
+}
+EXPORT_SYMBOL(gpio_cs42888_pdwn);
+
+static void gpio_usbotg_vbus_active(void)
+{
+	if (board_is_mx53_arm2()) {
+		/* MX53 ARM2 CPU board */
+		/* Enable OTG VBus with GPIO low */
+		gpio_set_value(ARM2_OTG_VBUS, 0);
+	} else  if (board_is_mx53_evk_a()) {
+		/* MX53 EVK board ver A*/
+		/* Enable OTG VBus with GPIO low */
+		gpio_set_value(EVK_OTG_VBUS, 0);
+	} else  if (board_is_mx53_evk_b()) {
+		/* MX53 EVK board ver B*/
+		/* Enable OTG VBus with GPIO high */
+		gpio_set_value(EVK_OTG_VBUS, 1);
+	}
+}
+
+static void gpio_usbotg_vbus_inactive(void)
+{
+	if (board_is_mx53_arm2()) {
+		/* MX53 ARM2 CPU board */
+		/* Disable OTG VBus with GPIO high */
+		gpio_set_value(ARM2_OTG_VBUS, 1);
+	} else  if (board_is_mx53_evk_a()) {
+		/* MX53 EVK board ver A*/
+		/* Disable OTG VBus with GPIO high */
+		gpio_set_value(EVK_OTG_VBUS, 1);
+	} else  if (board_is_mx53_evk_b()) {
+		/* MX53 EVK board ver B*/
+		/* Disable OTG VBus with GPIO low */
+		gpio_set_value(EVK_OTG_VBUS, 0);
+	}
+}
+
+static void mx53_gpio_usbotg_driver_vbus(bool on)
+{
+	if (on)
+		gpio_usbotg_vbus_active();
+	else
+		gpio_usbotg_vbus_inactive();
+}
+
+static void mx53_gpio_host1_driver_vbus(bool on)
+{
+	if (on)
+		gpio_set_value(EVK_USBH1_VBUS, 1);
+	else
+		gpio_set_value(EVK_USBH1_VBUS, 0);
+}
+
 static void adv7180_pwdn(int pwdn)
 {
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
+	gpio_request(MX53_TVIN_PWR, "tvin-pwr");
+	gpio_direction_output(MX53_TVIN_PWR, 0);
 	if (pwdn)
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
+		gpio_set_value(MX53_TVIN_PWR, 0);
 	else
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 1);
+		gpio_set_value(MX53_TVIN_PWR, 1);
 }
 
 static struct mxc_tvin_platform_data adv7180_data = {
@@ -379,9 +868,9 @@ device_initcall(mxc_init_fb);
 
 static void camera_pwdn(int pwdn)
 {
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), pwdn);
+	gpio_request(MX53_TVIN_PWR, "tvin-pwr");
+	gpio_direction_output(MX53_TVIN_PWR, 0);
+	gpio_set_value(MX53_TVIN_PWR, pwdn);
 }
 
 static struct mxc_camera_platform_data camera_data = {
@@ -417,7 +906,7 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	{
 	 .type = "tsc2007",
 	 .addr = 0x48,
-	 .irq  = IOMUX_TO_IRQ(MX53_PIN_EIM_A25),
+	 .irq  = IOMUX_TO_IRQ_V3(EVK_TS_INT),
 	},
 	{
 	 .type = "backlight-i2c",
@@ -468,9 +957,9 @@ static int sdhc_write_protect(struct device *dev)
 
 	if (!board_is_mx53_arm2()) {
 		if (to_platform_device(dev)->id == 0)
-			rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14));
+			rc = gpio_get_value(EVK_SD1_WP);
 		else
-			rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12));
+			rc = gpio_get_value(EVK_SD3_WP);
 	}
 
 	return rc;
@@ -481,14 +970,14 @@ static unsigned int sdhc_get_card_det_status(struct device *dev)
 	int ret;
 	if (board_is_mx53_arm2()) {
 		if (to_platform_device(dev)->id == 0)
-			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+			ret = gpio_get_value(ARM2_SD1_CD);
 		else
 			ret = 1;
 	} else {
 		if (to_platform_device(dev)->id == 0) {
-			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));
+			ret = gpio_get_value(EVK_SD1_CD);
 		} else{		/* config the det pin for SDHC3 */
-			ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));
+			ret = gpio_get_value(EVK_SD3_CD);
 			}
 	}
 
@@ -684,7 +1173,7 @@ return 0;
 
 static int headphone_det_status(void)
 {
-	return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0);
+	return (gpio_get_value(MX53_HP_DETECT) == 0);
 }
 
 static int mxc_sgtl5000_init(void);
@@ -693,7 +1182,7 @@ static struct mxc_audio_platform_data sgtl5000_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 5,
-	.hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5),
+	.hp_irq = IOMUX_TO_IRQ(MX53_HP_DETECT),
 	.hp_status = headphone_det_status,
 	.amp_enable = mxc_sgtl5000_amp_enable,
 	.init = mxc_sgtl5000_init,
@@ -817,7 +1306,6 @@ static struct platform_device mxc_alsa_surround_device = {
 };
 
 static int __initdata mxc_apc_on = { 0 };	/* OFF: 0 (default), ON: 1 */
-
 static int __init apc_setup(char *__unused)
 {
 	mxc_apc_on = 1;
@@ -826,6 +1314,22 @@ static int __init apc_setup(char *__unused)
 }
 __setup("apc", apc_setup);
 
+static int __initdata enable_w1 = { 0 };
+static int __init w1_setup(char *__unused)
+{
+	enable_w1 = 1;
+	return cpu_is_mx53();
+}
+__setup("w1", w1_setup);
+
+
+static int __initdata enable_spdif = { 0 };
+static int __init spdif_setup(char *__unused)
+{
+	enable_spdif = 1;
+	return 1;
+}
+__setup("spdif", spdif_setup);
 
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
@@ -911,8 +1415,140 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 #endif
 	}
 }
-extern void mx53_gpio_usbotg_driver_vbus(bool on);
-extern void mx53_gpio_host1_driver_vbus(bool on);
+
+static void __init mx53_evk_io_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx53common_pads,
+					ARRAY_SIZE(mx53common_pads));
+
+	if (board_is_mx53_arm2()) {
+		/* MX53 ARM2 CPU board */
+		pr_info("MX53 ARM2 board \n");
+		mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads,
+					ARRAY_SIZE(mx53arm2_pads));
+
+		/* Config GPIO for OTG VBus */
+		gpio_request(ARM2_OTG_VBUS, "otg-vbus");
+		gpio_direction_output(ARM2_OTG_VBUS, 1);
+
+		gpio_request(ARM2_SD1_CD, "sdhc1-cd");
+		gpio_direction_input(ARM2_SD1_CD);	/* SD1 CD */
+
+		gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast");
+		gpio_direction_output(ARM2_LCD_CONTRAST, 1);
+	} else {
+		/* MX53 EVK board */
+		pr_info("MX53 EVK board \n");
+		mxc_iomux_v3_setup_multiple_pads(mx53evk_pads,
+					ARRAY_SIZE(mx53evk_pads));
+
+		/* Host1 Vbus with GPIO high */
+		gpio_request(EVK_USBH1_VBUS, "usbh1-vbus");
+		gpio_direction_output(EVK_USBH1_VBUS, 1);
+		/* shutdown the Host1 Vbus when system bring up,
+		* Vbus will be opened in Host1 driver's probe function */
+		gpio_set_value(EVK_USBH1_VBUS, 0);
+
+		/* USB HUB RESET - De-assert USB HUB RESET_N */
+		gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset");
+		gpio_direction_output(EVK_USB_HUB_RESET, 0);
+		msleep(1);
+		gpio_set_value(EVK_USB_HUB_RESET, 1);
+
+		/* Config GPIO for OTG VBus */
+		gpio_request(EVK_OTG_VBUS, "otg-vbus");
+		gpio_direction_output(EVK_OTG_VBUS, 0);
+		if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/
+			gpio_set_value(EVK_OTG_VBUS, 1);
+		else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/
+			gpio_set_value(EVK_OTG_VBUS, 0);
+
+		gpio_request(EVK_SD1_CD, "sdhc1-cd");
+		gpio_direction_input(EVK_SD1_CD);	/* SD1 CD */
+		gpio_request(EVK_SD1_WP, "sdhc1-wp");
+		gpio_direction_input(EVK_SD1_WP);	/* SD1 WP */
+
+		/* SD3 CD */
+		gpio_request(EVK_SD3_CD, "sdhc3-cd");
+		gpio_direction_input(EVK_SD3_CD);
+
+		/* SD3 WP */
+		gpio_request(EVK_SD3_CD, "sdhc3-wp");
+		gpio_direction_input(EVK_SD3_WP);
+
+		/* reset FEC PHY */
+		gpio_request(EVK_FEC_PHY_RESET, "fec-phy-reset");
+		gpio_direction_output(EVK_FEC_PHY_RESET, 0);
+		msleep(1);
+		gpio_set_value(EVK_FEC_PHY_RESET, 1);
+
+		gpio_request(MX53_ESAI_RESET, "fesai-reset");
+		gpio_direction_output(MX53_ESAI_RESET, 0);
+	}
+
+	/* DVI Detect */
+	gpio_request(MX53_DVI_DETECT, "dvi-detect");
+	gpio_direction_input(MX53_DVI_DETECT);
+	/* DVI Reset - Assert for i2c disabled mode */
+	gpio_request(MX53_DVI_RESET, "dvi-reset");
+	gpio_set_value(MX53_DVI_RESET, 0);
+
+	/* DVI Power-down */
+	gpio_request(MX53_DVI_PD, "dvi-pd");
+	gpio_direction_output(MX53_DVI_PD, 1);
+
+	/* DVI I2C enable */
+	gpio_request(MX53_DVI_I2C, "dvi-i2c");
+	gpio_direction_output(MX53_DVI_I2C, 0);
+
+	mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads,
+					ARRAY_SIZE(mx53_nand_pads));
+
+	gpio_request(MX53_PMIC_INT, "pmic-int");
+	gpio_direction_input(MX53_PMIC_INT);	/*PMIC_INT*/
+
+	/* headphone_det_b */
+	gpio_request(MX53_HP_DETECT, "hp-detect");
+	gpio_direction_input(MX53_HP_DETECT);
+
+	/* power key */
+
+	/* LCD related gpio */
+
+	/* Camera reset */
+	gpio_request(MX53_CAM_RESET, "cam-reset");
+	gpio_direction_output(MX53_CAM_RESET, 1);
+
+	/* TVIN reset */
+	gpio_request(MX53_TVIN_RESET, "tvin-reset");
+	gpio_direction_output(MX53_TVIN_RESET, 0);
+	msleep(5);
+	gpio_set_value(MX53_TVIN_RESET, 1);
+
+	/* CAN1 enable GPIO*/
+	gpio_request(MX53_CAN1_EN1, "can1-en1");
+	gpio_direction_output(MX53_CAN1_EN1, 0);
+
+	gpio_request(MX53_CAN1_EN2, "can1-en2");
+	gpio_direction_output(MX53_CAN1_EN2, 0);
+
+	/* CAN2 enable GPIO*/
+	gpio_request(MX53_CAN2_EN1, "can2-en1");
+	gpio_direction_output(MX53_CAN2_EN1, 0);
+
+	gpio_request(MX53_CAN2_EN2, "can2-en2");
+	gpio_direction_output(MX53_CAN2_EN2, 0);
+
+	if (enable_spdif) {
+		struct pad_desc spdif_pin = MX53_PAD_GPIO_19__SPDIF_TX1;
+		mxc_iomux_v3_setup_pad(&spdif_pin);
+	} else {
+		/* GPIO for 12V */
+		gpio_request(MX53_12V_EN, "12v-en");
+		gpio_direction_output(MX53_12V_EN, 0);
+	}
+}
+
 /*!
  * Board specific initialization.
  */
@@ -925,17 +1561,17 @@ static void __init mxc_board_init(void)
 
 	/* SD card detect irqs */
 	if (board_is_mx53_arm2()) {
-		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_GPIO_1);
-		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_GPIO_1);
+		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARM2_SD1_CD);
+		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARM2_SD1_CD);
 		mmc3_data.card_inserted_state = 1;
 		mmc3_data.status = NULL;
 		mmc3_data.wp_status = NULL;
 		mmc1_data.wp_status = NULL;
 	} else {
-		mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11);
-		mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11);
-		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13);
-		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13);
+		mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD3_CD);
+		mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD3_CD);
+		mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD1_CD);
+		mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD1_CD);
 	}
 
 	mxc_cpu_common_init();
diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c
deleted file mode 100644
index caeee73ea414..000000000000
--- a/arch/arm/mach-mx5/mx53_evk_gpio.c
+++ /dev/null
@@ -1,1323 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-
-#include "iomux.h"
-#include "mx53_pins.h"
-
-/*!
- * @file mach-mx53/mx53_evk_gpio.c
- *
- * @brief This file contains all the GPIO setup functions for the board.
- *
- * @ingroup GPIO
- */
-
-static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
-	{
-	 MX53_PIN_EIM_WAIT, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_EIM_A25, IOMUX_CONFIG_ALT6,
-	 },
-	{
-	 MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4,
-	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
-	 MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4,
-	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
-	 MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4,
-	 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH,
-	 MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT4,
-	 },
-	{
-	 MX53_PIN_EIM_D24, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_EIM_D26, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT4,
-	 },
-	{
-	 MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT4,
-	 },
-	{
-	 MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_ATA_CS_0, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_CS_1, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_ATA_DA_1, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_ATA_DATA4, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_ATA_DATA6, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_ATA_DATA12, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_ATA_DATA13, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_ATA_DATA14, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_ATA_DATA15, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_ATA_DIOR, IOMUX_CONFIG_ALT3,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	 INPUT_CTL_PATH3,
-	 },
-	{
-	 MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_INTRQ, IOMUX_CONFIG_ALT3,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2,
-	 },
-	{
-	 MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT1,
-	 },
-	{ /* UART1 Tx */
-	 MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 },
-	{ /* UART1 Rx */
-	 MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	},
-	{
-	 MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT7,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-	 PAD_CTL_360K_PD),
-	 MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH2,
-	 },
-	{
-	 MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT7,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-	 PAD_CTL_360K_PD),
-	 MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH2,
-	 },
-	{
-	 MX53_PIN_GPIO_4, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_GPIO_6, IOMUX_CONFIG_ALT7,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-	 PAD_CTL_360K_PD),
-	 MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH2,
-	 },
-	{
-	 MX53_PIN_GPIO_7, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_GPIO_8, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* CAN1-TX */
-	 MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN1-RX */
-	 MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* CAN1 -- EN */
-	 MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN1 -- STBY */
-	 MX53_PIN_GPIO_17, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN1 -- NERR */
-	 MX53_PIN_GPIO_5, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	 },
-	{ /* CAN2-TX */
-	 MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN2-RX */
-	 MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* CAN2 -- EN */
-	 MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN2 -- STBY */
-	 MX53_PIN_GPIO_14, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{ /* CAN2 -- NERR */
-	 MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{
-	 MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* ESAI reset */
-	 MX53_PIN_GPIO_12, IOMUX_CONFIG_ALT0,
-	(PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-	  PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	  PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO,
-	 },
-	{
-	 MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1,
-	 },
-	{	/* DI0 display clock */
-	 MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
-	 },
-	{	/* DI0 data enable */
-	 MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW),
-	 },
-	{	/* DI0 HSYNC */
-	 MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{	/* DI0 VSYNC */
-	 MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW),
-	 },
-	{
-	 MX53_PIN_LVDS0_TX3_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS0_CLK_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS0_TX2_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS0_TX1_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS0_TX0_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS1_TX3_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS1_CLK_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS1_TX2_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS1_TX1_P, IOMUX_CONFIG_ALT1,
-	 },
-	{
-	 MX53_PIN_LVDS1_TX0_P, IOMUX_CONFIG_ALT1,
-	 },
-	{ /* audio and CSI clock out */
-	 MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3,
-	 },
-	{
-	 MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D14, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D15, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D16, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D17, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D18, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{
-	 MX53_PIN_CSI0_D19, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
-	 PAD_CTL_DRV_LOW,
-	 },
-	{	/* Camera VSYNC */
-	 MX53_PIN_CSI0_VSYNC, IOMUX_CONFIG_ALT0,
-	 },
-	{	/* Camera HSYNC */
-	 MX53_PIN_CSI0_MCLK, IOMUX_CONFIG_ALT0,
-	 },
-	{	/* Camera pixclk */
-	 MX53_PIN_CSI0_PIXCLK, IOMUX_CONFIG_ALT0,
-	 },
-	{	/* Camera low power */
-	 MX53_PIN_CSI0_D5, IOMUX_CONFIG_ALT1,
-	 },
-	/* esdhc1 */
-	{
-	 MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	 {
-	 MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	 {
-	 MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	 {
-	 MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	/* esdhc3 */
-	{
-	 MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{
-	 MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH
-	  | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE
-	  | PAD_CTL_SRE_FAST),
-	 },
-	{ /* FEC pins */
-	 MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH),
-	 MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	 },
-	{
-	 MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{
-	 MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{
-	 MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{
-	 MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{
-	 MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0,
-	(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{
-	 MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{
-	 MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{
-	 MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{
-	 MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	 { /* I2C1 SDA */
-	 MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	 { /* I2C1 SCL */
-	 MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	 { /* I2C2 SDA */
-	 MX53_PIN_KEY_ROW3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	 { /* I2C1 SCL */
-	 MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-};
-
-static struct mxc_iomux_pin_cfg __initdata mx53_evk_iomux_pins[] = {
-	{ /* USB OTG USB_OC */
-	 MX53_PIN_EIM_A24, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB OTG USB_PWR */
-	 MX53_PIN_EIM_A23, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* DISPB0_SER_CLK */
-	 MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT3,
-	 },
-	{ /* DI0_PIN1 */
-	 MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT3,
-	 },
-	{ /* DVI I2C ENABLE */
-	 MX53_PIN_EIM_D28, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* DVI DET */
-	 MX53_PIN_EIM_D31, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* SDHC1 SD_CD */
-	 MX53_PIN_EIM_DA13, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* SDHC1 SD_WP */
-	 MX53_PIN_EIM_DA14, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* SDHC3 SD_CD */
-	 MX53_PIN_EIM_DA11, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* SDHC3 SD_WP */
-	 MX53_PIN_EIM_DA12, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* PWM backlight */
-	 MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT4,
-	 },
-	 { /* USB HOST USB_PWR */
-	 MX53_PIN_ATA_DA_2, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB HOST USB_RST */
-	 MX53_PIN_CSI0_DATA_EN, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB HOST CARD_ON */
-	 MX53_PIN_EIM_DA15, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB HOST CARD_RST */
-	 MX53_PIN_ATA_DATA7, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB HOST WAN_WAKE */
-	 MX53_PIN_EIM_D25, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* FEC_RST */
-	MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1,
-	},
-};
-
-static struct mxc_iomux_pin_cfg __initdata mx53_arm2_iomux_pins[] = {
-	{ /* USB OTG USB_OC */
-	 MX53_PIN_EIM_D21, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* USB OTG USB_PWR */
-	 MX53_PIN_EIM_D22, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* SDHC1 SD_CD */
-	 MX53_PIN_GPIO_1, IOMUX_CONFIG_GPIO,
-	 },
-	{ /* gpio backlight */
-	 MX53_PIN_DI0_PIN4, IOMUX_CONFIG_GPIO,
-	},
-};
-
-static int __initdata enable_w1 = { 0 };
-static int __init w1_setup(char *__unused)
-{
-	enable_w1 = 1;
-	return cpu_is_mx53();
-}
-
-__setup("w1", w1_setup);
-
-static struct mxc_iomux_pin_cfg __initdata nand_iomux_pins[] = {
-	{
-	 MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU,
-	},
-	{
-	 MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU,
-	},
-	{
-	 MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-	{
-	 MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH,
-	},
-};
-
-static int __initdata enable_spdif = { 0 };
-static int __init spdif_setup(char *__unused)
-{
-	enable_spdif = 1;
-	return 1;
-}
-
-__setup("spdif", spdif_setup);
-
-void __init mx53_evk_io_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
-		mxc_request_iomux(mxc_iomux_pins[i].pin,
-				  mxc_iomux_pins[i].mux_mode);
-		if (mxc_iomux_pins[i].pad_cfg)
-			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
-					  mxc_iomux_pins[i].pad_cfg);
-		if (mxc_iomux_pins[i].in_select)
-			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
-					    mxc_iomux_pins[i].in_mode);
-	}
-
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		pr_info("MX53 ARM2 board \n");
-		for (i = 0; i < ARRAY_SIZE(mx53_arm2_iomux_pins); i++) {
-			mxc_request_iomux(mx53_arm2_iomux_pins[i].pin,
-					  mx53_arm2_iomux_pins[i].mux_mode);
-			if (mx53_arm2_iomux_pins[i].pad_cfg)
-				mxc_iomux_set_pad(mx53_arm2_iomux_pins[i].pin,
-						  mx53_arm2_iomux_pins[i].pad_cfg);
-			if (mx53_arm2_iomux_pins[i].in_select)
-				mxc_iomux_set_input(mx53_arm2_iomux_pins[i].in_select,
-						    mx53_arm2_iomux_pins[i].in_mode);
-		}
-
-		/* Config GPIO for OTG VBus */
-		mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1);
-
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));	/* SD1 CD */
-
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), "gpio4_20");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 1);
-	} else {
-		/* MX53 EVK board */
-		pr_info("MX53 EVK board \n");
-			for (i = 0; i < ARRAY_SIZE(mx53_evk_iomux_pins); i++) {
-			mxc_request_iomux(mx53_evk_iomux_pins[i].pin,
-					  mx53_evk_iomux_pins[i].mux_mode);
-			if (mx53_evk_iomux_pins[i].pad_cfg)
-				mxc_iomux_set_pad(mx53_evk_iomux_pins[i].pin,
-						  mx53_evk_iomux_pins[i].pad_cfg);
-			if (mx53_evk_iomux_pins[i].in_select)
-				mxc_iomux_set_input(mx53_evk_iomux_pins[i].in_select,
-						    mx53_evk_iomux_pins[i].in_mode);
-		}
-		/* Host1 Vbus with GPIO high */
-		mxc_iomux_set_pad(MX53_PIN_ATA_DA_2, PAD_CTL_DRV_HIGH |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
-		/* shutdown the Host1 Vbus when system bring up,
-		 * Vbus will be opened in Host1 driver's probe function */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
-
-		/* USB HUB RESET - De-assert USB HUB RESET_N */
-		mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH |
-				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), "gpio5_20");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);
-
-		msleep(1);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);
-		msleep(1);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1);
-
-		/* Config GPIO for OTG VBus */
-		mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
-
-		if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
-		else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
-
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));	/* SD1 CD */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14), "gpio3_14");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14));	/* SD1 WP */
-
-		/* SD3 CD */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11), "gpio3_11");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));
-
-		/* SD3 WP */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12), "gpio3_12");
-		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));
-
-		/* reset FEC PHY */
-		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), "gpio7_6");
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
-		msleep(1);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1);
-
-		/* CS42888 reset GPIO */
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
-
-	}
-
-	/* DVI Detect */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31");
-	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31));
-	/* DVI Reset - Assert for i2c disabled mode */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0");
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
-	/* DVI Power-down */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1);
-	/* DVI I2C enable */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
-
-	for (i = 0; i <  ARRAY_SIZE(nand_iomux_pins); i++) {
-		mxc_request_iomux(nand_iomux_pins[i].pin,
-					nand_iomux_pins[i].mux_mode);
-		if (nand_iomux_pins[i].pad_cfg)
-			mxc_iomux_set_pad(nand_iomux_pins[i].pin,
-					nand_iomux_pins[i].pad_cfg);
-		if (nand_iomux_pins[i].in_select)
-			mxc_iomux_set_input(nand_iomux_pins[i].in_select,
-					nand_iomux_pins[i].in_mode);
-	}
-
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11");
-	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16));	/*PMIC_INT*/
-
-	/* headphone_det_b */
-	mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU);
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5), "gpio2_5");
-	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5));
-
-	/* power key */
-
-	/* LCD related gpio */
-
-	/* Camera reset */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), "gpio4_0");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1);
-
-	/* TVIN reset */
-	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), "gpio5_25");
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
-	msleep(5);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 1);
-
-	/* CAN1 enable GPIO*/
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
-
-	/* CAN2 enable GPIO*/
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
-
-	if (enable_spdif) {
-		mxc_free_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1);
-		mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX53_PIN_GPIO_19,
-			PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-			PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
-			PAD_CTL_PKE_ENABLE);
-	} else {
-		/* GPIO for CAN 12V */
-		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
-	}
-}
-
-/* workaround for ecspi chipselect pin may not keep correct level when idle */
-void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			/* de-select SS1 of instance: ecspi1. */
-			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
-			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
-					  PAD_CTL_HYS_ENABLE |
-					  PAD_CTL_PKE_ENABLE |
-					  PAD_CTL_PUE_PULL |
-					  PAD_CTL_100K_PU |
-					  PAD_CTL_DRV_HIGH);
-
-			/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
-			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
-			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
-					  PAD_CTL_HYS_ENABLE |
-					  PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_input(
-				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-					  INPUT_CTL_PATH3);
-			break;
-		case 0x2:
-			/* de-select SS0 of instance: ecspi1. */
-			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
-			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
-					  PAD_CTL_HYS_ENABLE |
-					  PAD_CTL_PKE_ENABLE |
-					  PAD_CTL_PUE_PULL |
-					  PAD_CTL_100K_PU |
-					  PAD_CTL_DRV_HIGH);
-			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
-			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
-					  PAD_CTL_HYS_ENABLE |
-					  PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_input(
-				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-					  INPUT_CTL_PATH3);
-
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_active);
-
-void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		switch (chipselect) {
-		case 0x1:
-			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_D19,
-					  IOMUX_CONFIG_GPIO);
-			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO);
-			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
-			break;
-		case 0x2:
-			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_EB2,
-					  IOMUX_CONFIG_GPIO);
-			mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_GPIO);
-			mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
-			break;
-		default:
-			break;
-		}
-		break;
-	case 2:
-		break;
-	case 3:
-		break;
-	default:
-		break;
-	}
-}
-EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_inactive);
-
-void flexcan_xcvr_enable(int id, int en)
-{
-	static int pwdn;
-	if (id < 0 || id > 1)
-		return;
-
-	if (en) {
-		if (!(pwdn++))
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 1);
-
-		if (id == 0) {
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 1);
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 1);
-		} else {
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 1);
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 1);
-		}
-
-	} else {
-		if (!(--pwdn))
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
-
-		if (id == 0) {
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
-		} else {
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
-			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
-		}
-	}
-}
-EXPORT_SYMBOL(flexcan_xcvr_enable);
-
-void gpio_lcd_active(void)
-{
-/* TO DO */
-}
-EXPORT_SYMBOL(gpio_lcd_active);
-
-void gpio_activate_esai_ports(void)
-{
-	unsigned int pad_val;
-
-	/* ESAI1-HCKR */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT2);
-	/* ESAI1-SCKR */
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT2);
-	/* ESAI1-FSR */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT2);
-	/* ESAI1-HCKT */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT2);
-	/* ESAI1-SCKT */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT2);
-	/* ESAI1-FST */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT2);
-	/* ESAI1-TX5-RX0 */
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT2);
-	/* ESAI1-TX4-RX1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT2);
-	/* ESAI1-TX3-RX2 */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT2);
-	/* ESAI1-TX2-RX3 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT2);
-	/* ESAI1-TX1 */
-	mxc_request_iomux(MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3);
-	/* ESAI1-TX0 */
-	mxc_request_iomux(MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3);
-
-	pad_val = PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-		    PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-		    PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE;
-
-	/* ESAI1-HCKR */
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, pad_val);
-	/* ESAI1-SCKR */
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, pad_val);
-	/* ESAI1-FSR */
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, pad_val);
-	/* ESAI1-HCKT */
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, pad_val);
-	/* ESAI1-SCKT */
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, pad_val);
-	/* ESAI1-FST */
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, pad_val);
-	/* ESAI1-TX5-RX0 */
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, pad_val);
-	/* ESAI1-TX4-RX1 */
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, pad_val);
-	/* ESAI1-TX3-RX2 */
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, pad_val);
-	/* ESAI1-TX2-RX3 */
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, pad_val);
-	/* ESAI1-TX1 */
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS3, pad_val);
-	/* ESAI1-TX0 */
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS2, pad_val);
-
-	/* ESAI1-HCKR */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-SCKR */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-FSR */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-HCKT */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-SCKT */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-FST */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX5-RX0 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX4-RX1 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX3-RX2 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX2-RX3 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX1 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	/* ESAI1-TX0 */
-	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-
-}
-EXPORT_SYMBOL(gpio_activate_esai_ports);
-
-void gpio_cs42888_pdwn(int pdwn)
-{
-	if (pdwn)
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
-	else
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 1);
-}
-EXPORT_SYMBOL(gpio_cs42888_pdwn);
-
-static void gpio_usbotg_vbus_active(void)
-{
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		/* Enable OTG VBus with GPIO low */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
-	} else  if (board_is_mx53_evk_a()) {
-		/* MX53 EVK board ver A*/
-		/* Enable OTG VBus with GPIO low */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
-	} else  if (board_is_mx53_evk_b()) {
-		/* MX53 EVK board ver B*/
-		/* Enable OTG VBus with GPIO high */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
-	}
-}
-
-static void gpio_usbotg_vbus_inactive(void)
-{
-	if (board_is_mx53_arm2()) {
-		/* MX53 ARM2 CPU board */
-		/* Disable OTG VBus with GPIO high */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1);
-	} else  if (board_is_mx53_evk_a()) {
-		/* MX53 EVK board ver A*/
-		/* Disable OTG VBus with GPIO high */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
-	} else  if (board_is_mx53_evk_b()) {
-		/* MX53 EVK board ver B*/
-		/* Disable OTG VBus with GPIO low */
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
-	}
-}
-
-
-void mx53_gpio_usbotg_driver_vbus(bool on)
-{
-	if (on)
-		gpio_usbotg_vbus_active();
-	else
-		gpio_usbotg_vbus_inactive();
-}
-EXPORT_SYMBOL(mx53_gpio_usbotg_driver_vbus);
-
-void mx53_gpio_host1_driver_vbus(bool on)
-{
-	if (on)
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
-	else
-		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
-}
-EXPORT_SYMBOL(mx53_gpio_host1_driver_vbus);
diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
index f8ec651cd459..445ab10f099a 100644
--- a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c
@@ -23,8 +23,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13892/core.h>
 #include <mach/irqs.h>
-#include "iomux.h"
-#include "mx53_pins.h"
+
+#include <mach/iomux-mx53.h>
 
 /*
  * Convenience conversion.
@@ -337,7 +337,7 @@ static struct mc13892_platform_data mc13892_plat = {
 
 static struct i2c_board_info __initdata mc13892_i2c_device = {
 	I2C_BOARD_INFO("mc13892", 0x08),
-	.irq = IOMUX_TO_IRQ(MX53_PIN_GPIO_16),
+	.irq = IOMUX_TO_IRQ_V3(203),
 	.platform_data = &mc13892_plat,
 };
 
diff --git a/arch/arm/mach-mx5/mx53_pins.h b/arch/arm/mach-mx5/mx53_pins.h
deleted file mode 100644
index bf83e9870538..000000000000
--- a/arch/arm/mach-mx5/mx53_pins.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __ASM_ARCH_MXC_MX53_PINS_H__
-#define __ASM_ARCH_MXC_MX53_PINS_H__
-#include "iomux.h"
-
-/*!
- * @file arch-mxc/mx53_pins.h
- *
- * @brief MX53 I/O Pin List
- *
- * @ingroup GPIO_MX53
- */
-
-#ifndef __ASSEMBLY__
-
-#define PAD_I_START_MX53		0x348
-
-#define _MXC_BUILD_PIN_MX53(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START_MX53) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN_MX53(gp, gi, ga, mi, pi) \
-    _MXC_BUILD_PIN_MX53(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN_MX53(mi, pi) \
-    _MXC_BUILD_PIN_MX53(NON_GPIO_PORT, 0, 0, mi, pi)
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
-	MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN_MX53(3, 5, 1, 0x20, 0x348),
-	MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN_MX53(3, 6, 1, 0x24, 0x34C),
-	MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN_MX53(3, 7, 1, 0x28, 0x350),
-	MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN_MX53(3, 8, 1, 0x2C, 0x354),
-	MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN_MX53(3, 9, 1, 0x30, 0x358),
-	MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN_MX53(3, 10, 1, 0x34, 0x35C),
-	MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN_MX53(3, 11, 1, 0x38, 0x360),
-	MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN_MX53(3, 12, 1, 0x3C, 0x364),
-	MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN_MX53(3, 13, 1, 0x40, 0x368),
-	MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN_MX53(3, 14, 1, 0x44, 0x36C),
-	MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN_MX53(3, 15, 1, 0x48, 0x370),
-	MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x374),
-	MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN_MX53(3, 16, 1, 0x4C, 0x378),
-	MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN_MX53(3, 17, 1, 0x50, 0x37C),
-	MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN_MX53(3, 18, 1, 0x54, 0x380),
-	MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN_MX53(3, 19, 1, 0x58, 0x384),
-	MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN_MX53(3, 20, 1, 0x5C, 0x388),
-	MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN_MX53(3, 21, 1, 0x60, 0x38C),
-	MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN_MX53(3, 22, 1, 0x64, 0x390),
-	MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN_MX53(3, 23, 1, 0x68, 0x394),
-	MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN_MX53(3, 24, 1, 0x6C, 0x398),
-	MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN_MX53(3, 25, 1, 0x70, 0x39C),
-	MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN_MX53(3, 26, 1, 0x74, 0x3A0),
-	MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN_MX53(3, 27, 1, 0x78, 0x3A4),
-	MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN_MX53(3, 28, 1, 0x7C, 0x3A8),
-	MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN_MX53(3, 29, 1, 0x80, 0x3AC),
-	MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN_MX53(3, 30, 1, 0x84, 0x3B0),
-	MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN_MX53(3, 31, 1, 0x88, 0x3B4),
-	MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN_MX53(4, 5, 1, 0x8C, 0x3B8),
-	MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN_MX53(4, 6, 1, 0x90, 0x3BC),
-	MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN_MX53(4, 7, 1, 0x94, 0x3C0),
-	MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN_MX53(4, 8, 1, 0x98, 0x3C4),
-	MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN_MX53(4, 9, 1, 0x9C, 0x3C8),
-	MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN_MX53(4, 10, 1, 0xA0, 0x3CC),
-	MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN_MX53(4, 11, 1, 0xA4, 0x3D0),
-	MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN_MX53(4, 12, 1, 0xA8, 0x3D4),
-	MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN_MX53(4, 13, 1, 0xAC, 0x3D8),
-	MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN_MX53(4, 14, 1, 0xB0, 0x3DC),
-	MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN_MX53(4, 15, 1, 0xB4, 0x3E0),
-	MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN_MX53(4, 16, 1, 0xB8, 0x3E4),
-	MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN_MX53(4, 17, 1, 0xBC, 0x3E8),
-	MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN_MX53(4, 18, 1, 0xC0, 0x3EC),
-	MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN_MX53(4, 19, 1, 0xC4, 0x3F0),
-	MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN_MX53(4, 20, 1, 0xC8, 0x3F4),
-	MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN_MX53(4, 21, 1, 0xCC, 0x3F8),
-	MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN_MX53(4, 22, 1, 0xD0, 0x3FC),
-	MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN_MX53(4, 23, 1, 0xD4, 0x400),
-	MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN_MX53(4, 24, 1, 0xD8, 0x404),
-	MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN_MX53(4, 25, 1, 0xDC, 0x408),
-	MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN_MX53(4, 26, 1, 0xE0, 0x40C),
-	MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN_MX53(4, 27, 1, 0xE4, 0x410),
-	MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN_MX53(4, 28, 1, 0xE8, 0x414),
-	MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN_MX53(4, 29, 1, 0xEC, 0x418),
-	MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN_MX53(4, 30, 1, 0xF0, 0x41C),
-	MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN_MX53(4, 31, 1, 0xF4, 0x420),
-	MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN_MX53(5, 0, 1, 0xF8, 0x424),
-	MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN_MX53(5, 1, 1, 0xFC, 0x428),
-	MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN_MX53(5, 2, 1, 0x100, 0x42C),
-	MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN_MX53(5, 3, 1, 0x104, 0x430),
-	MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN_MX53(5, 4, 1, 0x108, 0x434),
-	MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN_MX53(5, 5, 1, 0x10C, 0x438),
-	MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x43C),
-	MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x440),
-	MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x444),
-	MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x448),
-	MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x44C),
-	MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x450),
-	MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x454),
-	MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN_MX53(4, 2, 1, 0x110, 0x458),
-	MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN_MX53(1, 30, 1, 0x114, 0x45C),
-	MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN_MX53(2, 16, 1, 0x118, 0x460),
-	MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN_MX53(2, 17, 1, 0x11C, 0x464),
-	MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN_MX53(2, 18, 1, 0x120, 0x468),
-	MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN_MX53(2, 19, 1, 0x124, 0x46C),
-	MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN_MX53(2, 20, 1, 0x128, 0x470),
-	MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN_MX53(2, 21, 1, 0x12C, 0x474),
-	MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN_MX53(2, 22, 1, 0x130, 0x478),
-	MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN_MX53(2, 23, 1, 0x134, 0x47C),
-	MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN_MX53(1, 31, 1, 0x138, 0x480),
-	MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN_MX53(2, 24, 1, 0x13C, 0x484),
-	MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN_MX53(2, 25, 1, 0x140, 0x488),
-	MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN_MX53(2, 26, 1, 0x144, 0x48C),
-	MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN_MX53(2, 27, 1, 0x148, 0x490),
-	MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN_MX53(2, 28, 1, 0x14C, 0x494),
-	MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN_MX53(2, 29, 1, 0x150, 0x498),
-	MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN_MX53(2, 30, 1, 0x154, 0x49C),
-	MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN_MX53(2, 31, 1, 0x158, 0x4A0),
-	MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x4A4),
-	MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN_MX53(4, 4, 1, 0x15C, 0x4A8),
-	MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN_MX53(5, 6, 1, 0x160, 0x4AC),
-	MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN_MX53(1, 16, 1, 0x164, 0x4B0),
-	MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN_MX53(1, 17, 1, 0x168, 0x4B4),
-	MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN_MX53(1, 18, 1, 0x16C, 0x4B8),
-	MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN_MX53(1, 19, 1, 0x170, 0x4BC),
-	MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN_MX53(1, 20, 1, 0x174, 0x4C0),
-	MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN_MX53(1, 21, 1, 0x178, 0x4C4),
-	MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN_MX53(1, 22, 1, 0x17C, 0x4C8),
-	MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX53(1, 23, 1, 0x180, 0x4CC),
-	MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX53(1, 24, 1, 0x184, 0x4D0),
-	MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX53(1, 25, 1, 0x188, 0x4D4),
-	MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN_MX53(1, 26, 1, 0x18C, 0x4D8),
-	MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX53(1, 27, 1, 0x190, 0x4DC),
-	MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x4E0),
-	MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN_MX53(1, 28, 1, 0x194, 0x4E4),
-	MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN_MX53(1, 29, 1, 0x198, 0x4E8),
-	MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN_MX53(2, 0, 1, 0x19C, 0x4EC),
-	MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN_MX53(2, 1, 1, 0x1A0, 0x4F0),
-	MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN_MX53(2, 2, 1, 0x1A4, 0x4F4),
-	MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN_MX53(2, 3, 1, 0x1A8, 0x4F8),
-	MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN_MX53(2, 4, 1, 0x1AC, 0x4FC),
-	MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN_MX53(2, 5, 1, 0x1B0, 0x500),
-	MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN_MX53(2, 6, 1, 0x1B4, 0x504),
-	MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN_MX53(2, 7, 1, 0x1B8, 0x508),
-	MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN_MX53(2, 8, 1, 0x1BC, 0x50C),
-	MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN_MX53(2, 9, 1, 0x1C0, 0x510),
-	MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN_MX53(2, 10, 1, 0x1C4, 0x514),
-	MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN_MX53(2, 11, 1, 0x1C8, 0x518),
-	MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN_MX53(2, 12, 1, 0x1CC, 0x51C),
-	MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN_MX53(2, 13, 1, 0x1D0, 0x520),
-	MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN_MX53(2, 14, 1, 0x1D4, 0x524),
-	MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN_MX53(2, 15, 1, 0x1D8, 0x528),
-	MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN_MX53(5, 12, 1, 0x1DC, 0x52C),
-	MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN_MX53(5, 13, 1, 0x1E0, 0x530),
-	MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN_MX53(4, 0, 1, 0x1E4, 0x534),
-	MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x538),
-	MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x53C),
-	MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN_MX53(5, 22, 0, 0x1EC, NON_PAD_I),
-	MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN_MX53(5, 24, 0, 0x1F0, NON_PAD_I),
-	MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN_MX53(5, 26, 0, 0x1F4, NON_PAD_I),
-	MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN_MX53(5, 28, 0, 0x1F8, NON_PAD_I),
-	MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN_MX53(5, 30, 0, 0x1FC, NON_PAD_I),
-	MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN_MX53(6, 22, 0, 0x200, NON_PAD_I),
-	MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN_MX53(6, 24, 0, 0x204, NON_PAD_I),
-	MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN_MX53(6, 26, 0, 0x208, NON_PAD_I),
-	MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN_MX53(6, 28, 0, 0x20C, NON_PAD_I),
-	MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN_MX53(6, 30, 0, 0x210, NON_PAD_I),
-	MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN_MX53(3, 0, 0, 0x214, 0x540),
-	MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN_MX53(3, 1, 0, 0x218, 0x544),
-	MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN_MX53(3, 2, 0, 0x21C, 0x548),
-	MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN_MX53(3, 3, 0, 0x220, 0x54C),
-	MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN_MX53(3, 4, 0, 0x224, 0x550),
-	MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x554),
-	MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x558),
-	MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x55C),
-	MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x560),
-	MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x564),
-	MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x568),
-	MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x56C),
-	MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x570),
-	MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x574),
-	MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x578),
-	MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x57C),
-	MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x580),
-	MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x584),
-	MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x588),
-	MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x58C),
-	MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x590),
-	MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x594),
-	MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x598),
-	MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x59C),
-	MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN_MX53(5, 7, 1, 0x228, 0x5A0),
-	MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN_MX53(5, 8 , 1, 0x22C, 0x5A4),
-	MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN_MX53(5, 9, 1, 0x230, 0x5A8),
-	MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN_MX53(5, 10, 1, 0x234, 0x5AC),
-	MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN_MX53(5, 11, 1, 0x238, 0x5B0),
-	MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN_MX53(5, 14, 1, 0x23C, 0x5B4),
-	MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN_MX53(5, 15, 1, 0x240, 0x5B8),
-	MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN_MX53(5, 16, 1, 0x244, 0x5BC),
-	MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x5C0),
-	MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN_MX53(0, 22, 1, 0x248, 0x5C4),
-	MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 23, 1, 0x24C, 0x5C8),
-	MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN_MX53(0, 24, 1, 0x250, 0x5CC),
-	MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN_MX53(0, 25, 1, 0x254, 0x5D0),
-	MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN_MX53(0, 26, 1, 0x258, 0x5D4),
-	MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN_MX53(0, 27, 1, 0x25C, 0x5D8),
-	MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN_MX53(0, 28, 1, 0x260, 0x5DC),
-	MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN_MX53(0, 29, 1, 0x264, 0x5E0),
-	MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN_MX53(0, 30, 1, 0x268, 0x5E4),
-	MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN_MX53(0, 31, 1, 0x26C, 0x5E8),
-	MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x5EC),
-	MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN_MX53(5, 17, 1, 0x270, 0x5F0),
-	MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN_MX53(5, 18, 1, 0x274, 0x5F4),
-	MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN_MX53(6, 0, 1, 0x278, 0x5F8),
-	MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN_MX53(6, 1, 1, 0x27C, 0x5FC),
-	MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN_MX53(6, 2, 1, 0x280, 0x600),
-	MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN_MX53(6, 3, 1, 0x284, 0x604),
-	MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN_MX53(6, 4, 1, 0x288, 0x608),
-	MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN_MX53(6, 5, 1, 0x28C, 0x60C),
-	MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN_MX53(6, 6, 1, 0x290, 0x610),
-	MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN_MX53(6, 7, 1, 0x294, 0x614),
-	MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN_MX53(6, 8, 1, 0x298, 0x618),
-	MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN_MX53(6, 9, 1, 0x29C, 0x61C),
-	MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN_MX53(6, 10, 1, 0x2A0, 0x620),
-	MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x624),
-	MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(1, 0, 1, 0x2A4, 0x628),
-	MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(1, 1, 1, 0x2A8, 0x62C),
-	MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(1, 2, 1, 0x2AC, 0x630),
-	MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(1, 3, 1, 0x2B0, 0x634),
-	MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN_MX53(1, 4, 1, 0x2B4, 0x638),
-	MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN_MX53(1, 5, 1, 0x2B8, 0x63C),
-	MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN_MX53(1, 6, 1, 0x2BC, 0x640),
-	MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN_MX53(1, 7, 1, 0x2C0, 0x644),
-	MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN_MX53(1, 8, 1, 0x2C4, 0x648),
-	MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN_MX53(1, 9, 1, 0x2C8, 0x64C),
-	MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN_MX53(1, 10, 1, 0x2CC, 0x650),
-	MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN_MX53(1, 11, 1, 0x2D0, 0x654),
-	MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN_MX53(1, 12, 1, 0x2D4, 0x658),
-	MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN_MX53(1, 13, 1, 0x2D8, 0x65C),
-	MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN_MX53(1, 14, 1, 0x2DC, 0x660),
-	MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN_MX53(1, 15, 1, 0x2E0, 0x664),
-	MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x668),
-	MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(0, 16, 1, 0x2E4, 0x66C),
-	MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(0, 17, 1, 0x2E8, 0x670),
-	MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN_MX53(0, 18, 1, 0x2EC, 0x674),
-	MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(0, 19, 1, 0x2F0, 0x678),
-	MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 20, 1, 0x2F4, 0x67C),
-	MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(0, 21, 1, 0x2F8, 0x680),
-	MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x684),
-	MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 10, 1, 0x2FC, 0x688),
-	MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN_MX53(0, 11, 1, 0x300, 0x68C),
-	MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(0, 12, 1, 0x304, 0x690),
-	MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(0, 13, 1, 0x308, 0x694),
-	MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(0, 14, 1, 0x30C, 0x698),
-	MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(0, 15, 1, 0x310, 0x69C),
-	MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6A0),
-	MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN_MX53(0, 0, 1, 0x314, 0x6A4),
-	MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN_MX53(0, 1, 1, 0x318, 0x6A8),
-	MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN_MX53(0, 9, 1, 0x31C, 0x6AC),
-	MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN_MX53(0, 3, 1, 0x320, 0x6B0),
-	MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN_MX53(0, 6, 1, 0x324, 0x6B4),
-	MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN_MX53(0, 2, 1, 0x328, 0x6B8),
-	MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN_MX53(0, 4, 1, 0x32C, 0x6BC),
-	MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN_MX53(0, 5, 1, 0x330, 0x6C0),
-	MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN_MX53(0, 7, 1, 0x334, 0x6C4),
-	MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN_MX53(0, 8, 1, 0x338, 0x6C8),
-	MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN_MX53(6, 11, 1, 0x33C, 0x6CC),
-	MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN_MX53(6, 12, 1, 0x340, 0x6D0),
-	MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN_MX53(6, 13, 1, 0x344, 0x6D4),
-	MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6D8),
-	MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6DC),
-	MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E0),
-	MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E4),
-	MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E8),
-	MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6EC),
-	MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6F0),
-	MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6F4),
-	MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6FC),
-	MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x708),
-	MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x70C),
-	MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x710),
-	MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x714),
-	MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x718),
-	MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x71C),
-	MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x720),
-	MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x724),
-	MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x728),
-	MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x72C),
-};
-
-/*!
- * various IOMUX input select register index
- */
-enum iomux_input_select_mx53 {
-	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT,		/*0x760*/
-	MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT,
-	MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,	/*0x780*/
-	MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
-
-	MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-	MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-	MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
-	MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,	/*0x7B0*/
-	MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT,		/*0x7E0*/
-	MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-	MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-	MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT,
-	MUX_IN_FEC_FEC_COL_SELECT_INPUT,	/*0x800*/
-	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT,
-	MUX_IN_GPC_PMIC_RDY_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT,
-	MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
-	MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
-	MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
-
-	MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT,	/*0x840*/
-	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-
-	MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
-	MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
-	MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
-
-	MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
-
-	MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
-	MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
-
-	MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT,	/*0x870*/
-	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-
-	MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
-	MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-	MUX_INPUT_NUM_MUX,
-};
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX53_PINS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
new file mode 100644
index 000000000000..864ac0288b67
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -0,0 +1,577 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX53_H__
+#define __MACH_IOMUX_MX53_H__
+
+#include <mach/iomux-v3.h>
+
+/*
+ * various IOMUX alternate output functions (1-7)
+ */
+typedef enum iomux_config {
+	IOMUX_CONFIG_ALT0,
+	IOMUX_CONFIG_ALT1,
+	IOMUX_CONFIG_ALT2,
+	IOMUX_CONFIG_ALT3,
+	IOMUX_CONFIG_ALT4,
+	IOMUX_CONFIG_ALT5,
+	IOMUX_CONFIG_ALT6,
+	IOMUX_CONFIG_ALT7,
+	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+#define IOMUX_TO_IRQ_V3(pin)	(MXC_GPIO_IRQ_START + pin)
+
+#define NON_MUX_I	0x3FF
+#define NON_PAD_I	0x7FF
+
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL	(PAD_CTL_DSE_MAX | PAD_CTL_PUS_22K_UP | \
+				PAD_CTL_SRE_FAST | PAD_CTL_DVS | \
+				PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX53_FEC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+			PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_DSE_HIGH)
+#define PAD_CTRL_1	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH)
+#define PAD_CTRL_2	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH)
+#define PAD_CTRL_3	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+					PAD_CTL_HYS)
+#define PAD_CTRL_4	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+					PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+#define PAD_CTRL_5	(PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+#define PAD_CTRL_6	(PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+#define PAD_CTRL_7	(PAD_CTL_DSE_HIGH | PAD_CTL_SRE_SLOW)
+#define PAD_CTRL_8	(PAD_CTL_HYS | PAD_CTL_PKE)
+
+#define PAD_CTRL_9	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+
+#define PAD_CTRL_10	(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
+
+#define PAD_CTRL_11	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
+#define PAD_CTRL_12	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+
+
+#define MX53_PAD_GPIO_19__GPIO_4_5		IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO_4_6		IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO_4_7		IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO_4_8		IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO_4_9		IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO_4_10		IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO_4_11	IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO_4_12		IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO_4_13	IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO_4_14		IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO_4_15	IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD	IOMUX_PAD(0x374, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16	IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO_4_17	IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO_4_18		IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO_4_19		IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO_4_20		IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO_4_21	IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO_4_22	IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO_4_23	IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO_4_24	IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO_4_25	IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO_4_26	IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO_4_27	IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO_4_28	IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO_4_29	IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO_4_30	IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO_4_31	IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO_5_5	IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO_5_6	IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO_5_7	IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO_5_8	IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO_5_9	IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO_5_10	IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO_5_11	IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO_5_12	IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO_5_13	IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO_5_14	IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO_5_15	IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__GPIO_5_16	IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__GPIO_5_17	IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18	IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__GPIO_5_19	IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20		IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, PAD_CTRL_12)
+#define MX53_PAD_CSI0_VSYNC__GPIO_5_21	IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D4__GPIO_5_22		IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_CSI0_D5__GPIO_5_23		IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D6__GPIO_5_24		IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_CSI0_D7__GPIO_5_25		IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D8__GPIO_5_26		IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D9__GPIO_5_27		IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D10__GPIO_5_28		IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D11__GPIO_5_29		IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D12__GPIO_5_30		IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D13__GPIO_5_31		IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D14__GPIO_6_0		IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D15__GPIO_6_1		IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D16__GPIO_6_2		IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D17__GPIO_6_3		IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D18__GPIO_6_4		IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D19__GPIO_6_5		IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_CSI0__NVCC_CSI0	IOMUX_PAD(0x43C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TMS__JTAG_TMS		IOMUX_PAD(0x440, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_MOD__JTAG_MOD		IOMUX_PAD(0x444, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB	IOMUX_PAD(0x448, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TDI__JTAG_TDI		IOMUX_PAD(0x44C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TCK__JTAG_TCK		IOMUX_PAD(0x450, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TDO__JTAG_TDO		IOMUX_PAD(0x454, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__GPIO_5_2		IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__GPIO_2_30		IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_EIM_D16__GPIO_3_16		IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO_3_17		IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO_3_18		IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__GPIO_3_19		IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_EIM_D20__GPIO_3_20		IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__GPIO_3_21		IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__GPIO_3_22		IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, PAD_CTRL_12)
+#define MX53_PAD_EIM_D23__GPIO_3_23		IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__GPIO_2_31		IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__GPIO_3_24		IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__GPIO_3_25		IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__GPIO_3_26		IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__GPIO_3_27		IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__GPIO_3_28		IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__GPIO_3_29		IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__GPIO_3_30		IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__GPIO_3_31		IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM1__NVCC_EIM1	IOMUX_PAD(0x4A4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__GPIO_5_4		IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__GPIO_6_6		IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, PAD_CTRL_12)
+#define MX53_PAD_EIM_A22__GPIO_2_16		IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__GPIO_2_17		IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__GPIO_2_18		IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__GPIO_2_19		IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__GPIO_2_20		IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__GPIO_2_21		IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__GPIO_2_22		IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__GPIO_2_23		IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__GPIO_2_24		IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__GPIO_2_25		IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__GPIO_2_26		IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__GPIO_2_27		IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM4__NVCC_EIM4	IOMUX_PAD(0x4E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPIO_2_28		IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__GPIO_2_29		IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__GPIO_3_0		IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__GPIO_3_1		IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__GPIO_3_2		IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__GPIO_3_3		IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__GPIO_3_4		IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__GPIO_3_5		IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__GPIO_3_6		IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__GPIO_3_7		IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__GPIO_3_8		IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__GPIO_3_9		IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__GPIO_3_10		IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__GPIO_3_11		IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__GPIO_3_12		IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__GPIO_3_13		IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__GPIO_3_14		IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__GPIO_3_15		IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__GPIO_6_12	IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__GPIO_6_13	IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__GPIO_5_0		IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_BCLK__EIM_BCLK		IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM7__NVCC_EIM7	IOMUX_PAD(0x53C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22	IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24	IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26	IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28	IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30	IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22	IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24	IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26	IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28	IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30	IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__GPIO_4_0	IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_11__GPIO_4_1	IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_12__GPIO_4_2	IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, \
+					PAD_CTRL_9 | PAD_CTRL_2)
+#define MX53_PAD_GPIO_13__GPIO_4_3	IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_14__GPIO_4_4	IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM3__DRAM_DQM3	IOMUX_PAD(0x554, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3	IOMUX_PAD(0x558, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1	IOMUX_PAD(0x55C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM2__DRAM_DQM2	IOMUX_PAD(0x560, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1	IOMUX_PAD(0x564, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2	IOMUX_PAD(0x568, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_RESET__DRAM_RESET	IOMUX_PAD(0x56C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1	IOMUX_PAD(0x570, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_CAS__DRAM_CAS	IOMUX_PAD(0x574, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0	IOMUX_PAD(0x578, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0	IOMUX_PAD(0x57C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0	IOMUX_PAD(0x580, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM0__DRAM_DQM0	IOMUX_PAD(0x584, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_RAS__DRAM_RAS	IOMUX_PAD(0x588, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0	IOMUX_PAD(0x58C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1	IOMUX_PAD(0x590, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM1__DRAM_DQM1	IOMUX_PAD(0x594, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ	IOMUX_PAD(0x598, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ	IOMUX_PAD(0x59C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__GPIO_6_7	IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__GPIO_6_8	IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__GPIO_6_9	IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__GPIO_6_10	IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__GPIO_6_11	IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__GPIO_6_14	IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__GPIO_6_15	IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__GPIO_6_16	IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_NANDF__NVCC_NANDF	IOMUX_PAD(0x5C0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__GPIO_1_22	IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__GPIO_1_23	IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__GPIO_1_24	IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__GPIO_1_25	IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__GPIO_1_26	IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__GPIO_1_27	IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__GPIO_1_28	IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__GPIO_1_29	IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__GPIO_1_30	IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__GPIO_1_31	IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_FEC__NVCC_FEC	IOMUX_PAD(0x5EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DIOW__GPIO_6_17	IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DMACK__GPIO_6_18	IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DMARQ__GPIO_7_0	IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1	IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_INTRQ__GPIO_7_2	IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DIOR__GPIO_7_3	IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_RESET_B__GPIO_7_4	IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_IORDY__GPIO_7_5	IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_0__GPIO_7_6	IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_1__GPIO_7_7	IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_2__GPIO_7_8	IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, PAD_CTRL_12)
+#define MX53_PAD_ATA_CS_0__GPIO_7_9	IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_CS_1__GPIO_7_10	IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_ATA2__NVCC_ATA2	IOMUX_PAD(0x624, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA0__GPIO_2_0	IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA1__GPIO_2_1	IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA2__GPIO_2_2	IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA3__GPIO_2_3	IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA4__GPIO_2_4	IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA5__GPIO_2_5	IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
+#define MX53_PAD_ATA_DATA6__GPIO_2_6	IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA7__GPIO_2_7	IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA8__GPIO_2_8	IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA9__GPIO_2_9	IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA10__GPIO_2_10	IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA11__GPIO_2_11	IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA12__GPIO_2_12	IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA13__GPIO_2_13	IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA14__GPIO_2_14	IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA15__GPIO_2_15	IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_ATA0__NVCC_ATA0	IOMUX_PAD(0x668, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO_1_16	IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO_1_17	IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO_1_18	IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO_1_19	IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO_1_20	IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO_1_21	IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_SD1__NVCC_SD1	IOMUX_PAD(0x684, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO_1_10	IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO_1_11	IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO_1_12	IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO_1_13	IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO_1_14	IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO_1_15	IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_SD2__NVCC_SD2	IOMUX_PAD(0x6A0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__GPIO_1_0	IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__GPIO_1_1	IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__GPIO_1_9	IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__GPIO_1_3	IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__GPIO_1_6	IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__GPIO_1_2	IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__GPIO_1_4	IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__GPIO_1_5	IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__GPIO_1_7	IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__GPIO_1_8	IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__GPIO_7_11	IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPIO_7_12	IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO_7_13	IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_GPIO__NVCC_GPIO	IOMUX_PAD(0x6D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_POR_B__POR_B	IOMUX_PAD(0x6DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_BOOT_MODE1__BOOT_MODE1	IOMUX_PAD(0x6E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_RESET_IN_B__RESET_IN_B	IOMUX_PAD(0x6E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_BOOT_MODE0__BOOT_MODE0	IOMUX_PAD(0x6E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_TEST_MODE__TEST_MODE	IOMUX_PAD(0x6EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_ADDDS__GRP_ADDDS	IOMUX_PAD(0x6F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL	IOMUX_PAD(0x6F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE	IOMUX_PAD(0x6FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRPK__GRP_DDRPK	IOMUX_PAD(0x708, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3	IOMUX_PAD(0x70C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS	IOMUX_PAD(0x710, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE	IOMUX_PAD(0x714, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B0DS__GRP_B0DS	IOMUX_PAD(0x718, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B1DS__GRP_B1DS	IOMUX_PAD(0x71C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_CTLDS__GRP_CTLDS	IOMUX_PAD(0x720, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE	IOMUX_PAD(0x724, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B2DS__GRP_B2DS	IOMUX_PAD(0x728, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B3DS__GRP_B3DS	IOMUX_PAD(0x72C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+
+/* NAND */
+#define MX53_PAD_NANDF_CLE__NANDF_CLE	IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_ALE__NANDF_ALE		IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_WP_B__NANDF_WP_B	IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, PAD_CTRL_11)
+#define MX53_PAD_NANDF_WE_B__NANDF_WE_B	IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_RE_B__NANDF_RE_B		IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_RB0__NANDF_RB0	IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, PAD_CTRL_11)
+#define MX53_PAD_NANDF_CS0__NANDF_CS0	IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_CS1__NANDF_CS1	IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_CS2__NANDF_CS2	IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_NANDF_CS3__NANDF_CS3	IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, PAD_CTRL_10)
+#define MX53_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, PAD_CTRL_10)
+
+/* SPI */
+#define MX53_PAD_EIM_EB2__CSPI_SS0		IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, PAD_CTRL_1)
+#define MX53_PAD_EIM_D19__CSPI_SS1		IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 3, PAD_CTRL_1)
+
+/* PWM */
+#define MX53_PAD_GPIO_1__PWMO	IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, NO_PAD_CTRL)
+
+/* Camera */
+#define MX53_PAD_CSI0_VSYNC__CSI0_VSYNC	IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK	IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__CSI0_HSYNC	IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
+
+/* IPU */
+#define MX53_PAD_CSI0_D12__CSI0_D12		IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D13__CSI0_D13		IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D14__CSI0_D14		IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D15__CSI0_D15		IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D16__CSI0_D16		IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D17__CSI0_D17		IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D18__CSI0_D18		IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D19__CSI0_D19		IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__SER_DISP0_CS	IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__DISPB0_SER_RS	IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__DI0_PIN11		IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__DI0_PIN12		IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__DI0_D0_CS		IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__DI0_D1_CS		IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__DI1_PIN7			IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__DI1_PIN8			IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__DISPB0_SER_CLK		IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__DISPB0_SER_DIN		IOMUX_PAD(0x478, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
+
+/* Display */
+#define MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK	IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, PAD_CTRL_5)
+#define MX53_PAD_DI0_PIN15__DI0_PIN15		IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, PAD_CTRL_6)
+#define MX53_PAD_DI0_PIN2__DI0_PIN2		IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DI0_PIN3__DI0_PIN3		IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT0__DISP0_DAT0	IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT1__DISP0_DAT1	IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT2__DISP0_DAT2	IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT3__DISP0_DAT3	IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT4__DISP0_DAT4	IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT5__DISP0_DAT5	IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT6__DISP0_DAT6	IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT7__DISP0_DAT7	IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT8__DISP0_DAT8	IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT9__DISP0_DAT9	IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT10__DISP0_DAT10	IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT11__DISP0_DAT11	IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT12__DISP0_DAT12	IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT13__DISP0_DAT13	IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT14__DISP0_DAT14	IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT15__DISP0_DAT15	IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT16__DISP0_DAT16	IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT17__DISP0_DAT17	IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT18__DISP0_DAT18	IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT19__DISP0_DAT19	IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT20__DISP0_DAT20	IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT21__DISP0_DAT21	IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT22__DISP0_DAT22	IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, PAD_CTRL_7)
+#define MX53_PAD_DISP0_DAT23__DISP0_DAT23	IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, PAD_CTRL_7)
+
+/* CAN*/
+#define MX53_PAD_KEY_COL2__TXCAN1			IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_KEY_ROW2__RXCAN1		IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, PAD_CTRL_3)
+#define MX53_PAD_KEY_COL4__TXCAN2			IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, PAD_CTRL_4)
+#define MX53_PAD_KEY_ROW4__RXCAN2		IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, PAD_CTRL_3)
+
+/* AUD5 */
+#define MX53_PAD_KEY_COL0__AUD5_TXC		IOMUX_PAD(0x34C, 0x24, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__AUD5_TXD		IOMUX_PAD(0x350, 0x28, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__AUD5_TXFS		IOMUX_PAD(0x354, 0x2C, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__AUD5_RXD		IOMUX_PAD(0x358, 0x30, 2, 0x0, 0, NO_PAD_CTRL)
+
+/* I2C1 */
+#define MX53_PAD_CSI0_D8__I2C1_SDA		IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, PAD_CTRL_9)
+#define MX53_PAD_CSI0_D9__I2C1_SCL		IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, PAD_CTRL_9)
+
+/* I2C2 */
+#define MX53_PAD_KEY_COL3__I2C2_SCL		IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, PAD_CTRL_9)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA		IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, PAD_CTRL_9)
+
+/* UART1 */
+#define MX53_PAD_CSI0_D10__UART1_TXD		IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_D11__UART1_RXD		IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+
+/* UART2 */
+#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD	IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DMARQ__UART2_TXD	IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DIOR__UART2_RTS		IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_INTRQ__UART2_CTS		IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, NO_PAD_CTRL)
+
+/* UART3 */
+#define MX53_PAD_ATA_CS_0__UART3_TXD		IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_CS_1__UART3_RXD		IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+
+/* CSPI */
+#define MX53_PAD_EIM_D16__CSPI1_SCLK		IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, PAD_CTRL_1)
+#define MX53_PAD_EIM_D17__CSPI1_MISO		IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, PAD_CTRL_1)
+#define MX53_PAD_EIM_D18__CSPI1_MOSI		IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, PAD_CTRL_1)
+
+/* LVDS0 */
+#define MX53_PAD_LVDS0_TX3_P__LVDS0_TX3	IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__LVDS0_CLK	IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__LVDS0_TX2	IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__LVDS0_TX1	IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__LVDS0_TX0	IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
+
+/* LVDS1 */
+#define MX53_PAD_LVDS1_TX3_P__LVDS1_TX3	IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__LVDS1_TX2	IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__LVDS1_CLK	IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__LVDS1_TX1	IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__LVDS1_TX0	IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
+
+/* SD1 */
+#define MX53_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__SD1_CMD		IOMUX_PAD(0x674, 0x2EC, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__SD1_CLK		IOMUX_PAD(0x67C, 0x2F4, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+
+/* SD2 */
+#define MX53_PAD_SD2_CLK__SD2_CLK		IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__SD2_CMD		IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__SD2_DAT0		IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__SD2_DAT1		IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__SD2_DAT2		IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__SD2_DAT3		IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA12__SD2_DAT4	IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA13__SD2_DAT5	IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA14__SD2_DAT6	IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA15__SD2_DAT7	IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, NO_PAD_CTRL)
+
+/* SD3 */
+#define MX53_PAD_ATA_DATA8__SD3_DAT0		IOMUX_PAD(0x648, 0x2C4, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA9__SD3_DAT1		IOMUX_PAD(0x64C, 0x2C8, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA10__SD3_DAT2	IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA11__SD3_DAT3	IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA0__SD3_DAT4		IOMUX_PAD(0x628, 0x2A4, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA1__SD3_DAT5		IOMUX_PAD(0x62C, 0x2A8, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA2__SD3_DAT6		IOMUX_PAD(0x630, 0x2AC, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_DATA3__SD3_DAT7		IOMUX_PAD(0x634, 0x2B0, 4, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_RESET_B__SD3_CMD	IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, \
+						MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_ATA_IORDY__SD3_CLK		IOMUX_PAD(0x60C, 0x28C, 2, \
+						0x0, 0, MX53_SDHC_PAD_CTRL)
+
+/* USB */
+#define MX53_PAD_EIM_A24__GPIO_5_4		IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
+
+/* FEC */
+#define MX53_PAD_FEC_MDIO__FEC_MDIO		IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, MX53_FEC_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__FEC_REF_CLK	IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, PAD_CTRL_8)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER	IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, PAD_CTRL_8)
+#define MX53_PAD_FEC_CRS_DV__FEC_CRS_DV	IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, PAD_CTRL_8)
+#define MX53_PAD_FEC_RXD1__FEC_RXD1		IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, PAD_CTRL_8)
+#define MX53_PAD_FEC_RXD0__FEC_RXD0		IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, PAD_CTRL_8)
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN	IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_FEC_TXD1__FEC_TXD1		IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_FEC_TXD0__FEC_TXD0		IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX53_PAD_FEC_MDC__FEC_MDC		IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX53_PAD_GPIO_0__SSI_EXT1_CLK		IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, NO_PAD_CTRL)
+
+/* MLB */
+#define MX53_PAD_GPIO_2__MLBDAT	IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, \
+					PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \
+					PAD_CTL_HYS)
+#define MX53_PAD_GPIO_3__MLBCLK	IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, \
+					PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \
+					PAD_CTL_HYS)
+#define MX53_PAD_GPIO_6__MLBSIG	IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, \
+					PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \
+					PAD_CTL_HYS)
+
+/* SPDIF */
+#define MX53_PAD_GPIO_19__SPDIF_TX1	IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, \
+					PAD_CTRL_3 | PAD_CTL_PUS_100K_UP)
+
+/* ESAI */
+#define MX53_PAD_FEC_MDIO__ESAI_SCKR		IOMUX_PAD(0x5C4, 0x248, 2, \
+							0x7DC, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_REF_CLK__ESAI_FSR	IOMUX_PAD(0x5C8, 0x24C, 2, \
+							0x7CC, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_RX_ER__ESAI_HCKR	IOMUX_PAD(0x5CC, 0x250, 2, \
+							0x7D4, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_CRS_DV__ESAI_SCKT	IOMUX_PAD(0x5D0, 0x254, 2, \
+							0x7E0, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_RXD1__ESAI_FST		IOMUX_PAD(0x5D4, 0x258, 2, \
+							0x7D0, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_RXD0__ESAI_HCKT		IOMUX_PAD(0x5D8, 0x25C, 2, \
+							0x7D8, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2	IOMUX_PAD(0x5DC, 0x260, 2, \
+							0x7F0, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_TXD1__ESAI_TX2_RX3	IOMUX_PAD(0x5E0, 0x264, 2, \
+							0x7EC, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_TXD0__ESAI_TX4_RX1	IOMUX_PAD(0x5E4, 0x268, 2, \
+							0x7F4, 0, PAD_CTRL_9)
+#define MX53_PAD_FEC_MDC__ESAI_TX5_RX0	IOMUX_PAD(0x5E8, 0x26C, 2, \
+							0x7F8, 0, PAD_CTRL_9)
+#define MX53_PAD_NANDF_CS2__ESAI_TX0		IOMUX_PAD(0x5B8, 0x240, 3, \
+							0x7E4, 0, PAD_CTRL_9)
+#define MX53_PAD_NANDF_CS3__ESAI_TX1		IOMUX_PAD(0x5BC, 0x244, 3, \
+							0x7E8, 0, PAD_CTRL_9)
+
+#endif /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..6beaf8cd69b5 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -75,7 +75,9 @@ struct pad_desc {
 #define PAD_CTL_PKE			(1 << 7)
 #define PAD_CTL_PUE			(1 << 6)
 #define PAD_CTL_PUS_100K_DOWN		(0 << 4)
+#define PAD_CTL_PUS_360K_DOWN		(0 << 4)
 #define PAD_CTL_PUS_47K_UP		(1 << 4)
+#define PAD_CTL_PUS_75K_UP		(1 << 4)
 #define PAD_CTL_PUS_100K_UP		(2 << 4)
 #define PAD_CTL_PUS_22K_UP		(3 << 4)