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authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-05-12 16:35:33 +0400
committerKumar Gala <galak@kernel.crashing.org>2008-05-13 08:53:48 -0500
commitf637ef8ea07d529418294a8e65e1be5b8db13454 (patch)
tree682fd5aa141a4fb3e39276de6e7a632bd942cd0a /arch
parent34b4a8731f50fb6fe772f1e47432bfb1da1f4edd (diff)
[POWERPC] 86xx: mpc8610_hpcd: fix second serial port
DIU platform code should not just write to the PIXIS' BRDCFG0 register, it should set and clear its own bits only, otherwise it will break firmware setup (in fact it breaks second uart). Also get rid of magic numbers in the related code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 782d1cb28b72..dea13208bf64 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -217,11 +217,21 @@ void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
}
}
+#define PX_BRDCFG0_DVISEL (1 << 3)
+#define PX_BRDCFG0_DLINK (1 << 4)
+#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
+
void mpc8610hpcd_set_monitor_port(int monitor_port)
{
- static const u8 bdcfg[] = {0xBD, 0xB5, 0xA5};
+ static const u8 bdcfg[] = {
+ PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
+ PX_BRDCFG0_DLINK,
+ 0,
+ };
+
if (monitor_port < 3)
- *pixis_bdcfg0 = bdcfg[monitor_port];
+ clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
+ bdcfg[monitor_port]);
}
void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)