diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2020-01-15 14:22:59 +0200 |
|---|---|---|
| committer | Robert Chiras <robert.chiras@nxp.com> | 2020-05-22 11:10:40 +0300 |
| commit | 02bfa9904b66e4f8a73956f50d989a1f25ed046c (patch) | |
| tree | c4f446d469a4705fd3cf2fb75976c75d0f272250 /arch | |
| parent | 57c96ce6a713eda64292708c1256914b8c94599e (diff) | |
LF-811-4: arm64: dts: imx8qxp: Add lcdif subsystem
Add the lcdif nodes for the LCDIF Display Controller subsystem.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi | 50 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 |
2 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi new file mode 100755 index 000000000000..1f6a55d1c577 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lcdif.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +/ { + lcdif_subsys: bus@5a180000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a180000 0x0 0x5a180000 0x500000>; + + ipg_dma_clk: clock-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "ipg_dma_clk"; + }; + + lcd_clk_lpcg: clock-controller@5a580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a580000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&ipg_dma_clk>; + bit-offset = <0 16>; + clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0>; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x5a180000 0x10000>; + clocks = <&lcd_clk_lpcg 0>, + <&lcd_clk_lpcg 1>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <804000000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 2fa28b89d52a..4495863a7c81 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -342,6 +342,7 @@ #include "imx8qxp-ss-hsio.dtsi" #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-lcdif.dtsi" #include "imx8qxp-ss-lvds.dtsi" #include "imx8qxp-ss-gpu.dtsi" |