ARM64: dts: add the hsio pcie support for imx8qm/qxp

Add the hsio pcie support for imx8qm/qxp.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

5 files changed, 159 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
new file mode 100644
index 000000000000..7bd40385570d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *	Richard Zhu <hongxing.zhu@nxp.com>
+ */
+#include <dt-bindings/soc/imx8_hsio.h>
+
+hsio_subsys: bus@5f000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	hsio_lpcg: clock-controller@5f050000 {
+		compatible = "fsl,imx8qm-lpcg-hsio", "fsl,imx8qxp-lpcg-hsio";
+		reg = <0x5f050000 0xc0000>;
+		#clock-cells = <1>;
+	};
+
+	hsio_gpr: hsio_gpr@0x5f110000 {
+		compatible = "fsl,imx8qm-hsio-gpr",
+			"fsl,imx6q-iomuxc-gpr", "syscon";
+		reg = <0x5f110000 0x70000>; /* csr regs, gpio */
+	};
+
+	pciea: pcie@0x5f000000 {
+		compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+		reg = <0x5f000000 0x10000>, /* Controller reg */
+		      <0x6ff00000 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+		ranges = <0x81000000 0 0x00000000 0x6ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x60000000 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 73 4>,
+				 <0 0 0 2 &gic 0 74 4>,
+				 <0 0 0 3 &gic 0 75 4>,
+				 <0 0 0 4 &gic 0 76 4>;
+		/*
+		 * Set these clocks in default, then clocks should be
+		 * refined for exact hw design of imx8 pcie.
+		 */
+		clocks = <&hsio_lpcg IMX_HSIO_LPCG_PCIEA_MSTR_AXI_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEA_SLV_AXI_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PHYX2_PCLK_0>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEA_PER_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEA_DBI_AXI_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+		power-domains = <&pd IMX_SC_R_PCIE_A>,
+				<&pd IMX_SC_R_SERDES_0>,
+				<&pd IMX_SC_R_HSIO_GPIO>;
+		power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+		local-addr = <0x40000000>;
+		status = "disabled";
+	};
+
+	pcieb: pcie@0x5f010000 {
+		compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+		reg = <0x5f010000 0x10000>, /* Controller reg */
+		      <0x7ff00000 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+		ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 105 4>,
+				 <0 0 0 2 &gic 0 106 4>,
+				 <0 0 0 3 &gic 0 107 4>,
+				 <0 0 0 4 &gic 0 108 4>;
+		/*
+		 * Set the clks/pds for imx8qxp in default, clks/pds should be
+		 * refined for exact hw design of imx8 pcie.
+		 For example, when hsio-cfg = <PCIEAX1PCIEBX1SATA>,
+		 set clks below.
+			clocks = <&hsio_lpcg IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
+				<&hsio_lpcg IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
+				<&hsio_lpcg IMX8QM_HSIO_PHY_X2_PCLK_1>,
+				<&hsio_lpcg IMX8QM_HSIO_PCIE_X1_PER_CLK>,
+				<&hsio_lpcg IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
+		 */
+		clocks = <&hsio_lpcg IMX_HSIO_LPCG_PCIEB_MSTR_AXI_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEB_SLV_AXI_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PHYX1_PCLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEB_PER_CLK>,
+			 <&hsio_lpcg IMX_HSIO_LPCG_PCIEB_DBI_AXI_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+		power-domains = <&pd IMX_SC_R_PCIE_B>,
+				<&pd IMX_SC_R_SERDES_1>,
+				<&pd IMX_SC_R_HSIO_GPIO>;
+		power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX2PCIEBX1>;
+		local-addr = <0x80000000>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 7b5541e191a8..6660964ffee8 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -67,6 +67,15 @@
 	};
 };
 
+&pciea{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
+	ext_osc = <1>;
+	status = "okay";
+};
+
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -114,6 +123,14 @@
 		>;
 	};
 
+	pinctrl_pciea: pcieagrp{
+		fsl,pins = <
+			IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27		0x06000021
+			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
+			IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
+		>;
+	};
+
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 218fa6903621..03dbc44fdbde 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/soc/imx8_hsio.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -188,4 +189,5 @@
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-lsio.dtsi"
+	#include "imx8-ss-hsio.dtsi"
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 8b05223db7b8..913fc835f8c5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -229,6 +229,18 @@
 	};
 };
 
+&pcieb{
+	compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
+	disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>;
+	disable2-gpio = <&pca9557_a 0 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+	ext_osc = <1>;
+	status = "okay";
+};
+
 &usdhc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -344,6 +356,14 @@
 		>;
 	};
 
+	pinctrl_pcieb: pcieagrp{
+		fsl,pins = <
+			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
+			IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01		0x06000021
+			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
+		>;
+	};
+
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 6efd18d7e768..794f8350596d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -264,6 +264,7 @@
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-ddr.dtsi"
 	#include "imx8-ss-lsio.dtsi"
+	#include "imx8-ss-hsio.dtsi"
 };
 
 &edma2 {