diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2020-09-22 14:49:09 +0800 |
|---|---|---|
| committer | Clark Wang <xiaoning.wang@nxp.com> | 2020-09-22 16:27:39 +0800 |
| commit | 3ac4d58d5ddbd5c2ebfcced5053d10e3883c2b3b (patch) | |
| tree | 9f83460c603d72ca63046b0edc83aa7ffc5de959 /arch | |
| parent | 41fae930efd1b0c4e78c7e3419b81dacee39097e (diff) | |
MLK-24827 ARM64: dts: imx8-dma: change spi and i2c irq number to non-combined
Combined interrupt number may cause unexcepted irq event when using DMA
and too many interrupts are generated.
So change all spi and i2c interrupts number to non-combined for
imx8qxp/8qm/8dxl.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 2 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index e33c2080ce3c..fd1faaca1909 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -24,7 +24,7 @@ dma_subsys: bus@5a000000 { reg = <0x5a000000 0x10000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&spi0_lpcg 0>, <&spi0_lpcg 1>; @@ -42,7 +42,7 @@ dma_subsys: bus@5a000000 { reg = <0x5a020000 0x10000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&spi2_lpcg 0>, <&spi2_lpcg 1>; @@ -60,7 +60,7 @@ dma_subsys: bus@5a000000 { reg = <0x5a030000 0x10000>; #address-cells = <1>; #size-cells = <0>; - interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&spi3_lpcg 0>, <&spi3_lpcg 1>; @@ -358,7 +358,7 @@ dma_subsys: bus@5a000000 { i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&i2c0_lpcg 0>, <&i2c0_lpcg 1>; @@ -371,7 +371,7 @@ dma_subsys: bus@5a000000 { i2c1: i2c@5a810000 { reg = <0x5a810000 0x4000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&i2c1_lpcg 0>, <&i2c1_lpcg 1>; @@ -384,7 +384,7 @@ dma_subsys: bus@5a000000 { i2c2: i2c@5a820000 { reg = <0x5a820000 0x4000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&i2c2_lpcg 0>, <&i2c2_lpcg 1>; @@ -397,7 +397,7 @@ dma_subsys: bus@5a000000 { i2c3: i2c@5a830000 { reg = <0x5a830000 0x4000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&i2c3_lpcg 0>, <&i2c3_lpcg 1>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index ae90a2e139e7..77b5e35d91ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -186,7 +186,7 @@ &lpspi3 { compatible = "fsl,imx8dxl-spi", "fsl,imx8qxp-spi", "fsl,imx7ulp-spi"; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; }; &flexcan1 { |