diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2019-09-26 17:47:56 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:59 +0800 |
| commit | 606755e45afb062ef340c511c931f764b71f825a (patch) | |
| tree | dc2789ea520bcf435a0424dd568327ccc8091b8c /arch | |
| parent | 04461eca5e1464f3e3c0ea47aa795ce0206c68e6 (diff) | |
ARM64: dts: imx8qm: enable ARC for HDMI Audio
enable ARC for HDMI Audio
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 47 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts | 18 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 16 |
3 files changed, 79 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 416f6cc700d5..24a63af43c49 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -204,7 +204,7 @@ audio_subsys: bus@59000000 { <&clk_dummy>, /* rxtx2 */ <&clk_dummy>, /* rxtx3 */ <&clk_dummy>, /* rxtx4 */ - <&clk_dummy>, /* rxtx5 */ + <&audio_ipg_clk>, /* rxtx5 */ <&clk_dummy>, /* rxtx6 */ <&clk_dummy>, /* rxtx7 */ <&clk_dummy>; /* spba */ @@ -225,6 +225,38 @@ audio_subsys: bus@59000000 { status = "disabled"; }; + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */ + clocks = <&spdif1_lpcg 1>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg 0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + status = "disabled"; + }; + sai0: sai@59040000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; @@ -458,6 +490,19 @@ audio_subsys: bus@59000000 { power-domains = <&pd IMX_SC_R_SPDIF_0>; }; + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + sai0_lpcg: clock-controller@59440000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59440000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts index 209f28d882c4..567aea715f39 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-hdmi.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "imx8qm-mek.dts" +#include "imx8qm-mek-rpmsg.dts" / { sound-hdmi-tx { @@ -17,6 +17,14 @@ protocol = <1>; hdmi-out; }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; }; &sai5 { @@ -48,3 +56,11 @@ lane-mapping = <0x93>; status = "okay"; }; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi index 382ce0bc8dcd..9b8653bd7c87 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -141,6 +141,16 @@ <&pd IMX_SC_R_AUDIO_PLL_1>; }; +&spdif1 { + power-domains = <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; +}; + &sai0 { power-domains = <&pd IMX_SC_R_SAI_0>, <&pd IMX_SC_R_DMA_2_CH12>, @@ -236,6 +246,12 @@ "spdif0_lpcg_gclkw"; }; +&spdif1_lpcg { + bit-offset = <20 16>; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; +}; + &sai0_lpcg { bit-offset = <16 0>; clock-output-names = "sai0_lpcg_mclk", |