diff options
author | Viorel Suman <viorel.suman@nxp.com> | 2020-04-02 13:06:07 +0300 |
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committer | Viorel Suman <viorel.suman@nxp.com> | 2020-04-15 14:50:28 +0300 |
commit | 8ee250e84feb88bf37b19874149f6ee1c8714865 (patch) | |
tree | b8af289bda83e63d50b41546efe38c67ec1f8b7f /arch | |
parent | dcc967d4990362df55a6a8b904f06b85d430ce24 (diff) |
MLK-23794 dts: arm64: imx8mp-ab2: enable HDMI SS
Enable HDMI SS.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'arch')
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 96 |
1 files changed, 92 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts index fd421b7e4a86..c6f7ba84781c 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -88,6 +88,26 @@ audio-cpu = <&sai3>; audio-codec = <&ak5552>; }; + + sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif3_disp>; + }; }; &{/busfreq} { @@ -475,7 +495,79 @@ status = "okay"; }; +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_vc8000e { + status = "okay"; +}; + +&gpu_3d { + status = "okay"; +}; + +&gpu_2d { + status = "okay"; +}; + +&ml_vipsi { + status = "okay"; +}; + +&mix_gpu_ml { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&hdmimix_clk { + status = "okay"; +}; + +&hdmimix_reset { + status = "okay"; +}; + +&hdmi_pavi { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&aud2htx { + status = "okay"; +}; + &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x40000019 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 @@ -621,10 +713,6 @@ pinctrl_xcvr: xcvrgrp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL 0x400001c3 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA 0x400001c3 - MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD 0x40000019 - MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC 0x40000019 MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK 0xd6 MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_IN 0xd6 MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUT 0xd6 |