arm64: imx8qxp.dtsi: Introduce LVDS subsystem support

This patch introduces i.MX8qxp LVDS subsystem support in device tree.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: update irqsteer to latest binding ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

3 files changed, 206 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi
index 287f6b628756..16150e0a6763 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi
@@ -117,9 +117,11 @@ dc_subsys: bus@56000000 {
 			reg = <0>;
 
 			dpu_disp0_lvds0_ch0: endpoint@0 {
+				remote-endpoint = <&ldb1_ch0>;
 			};
 
 			dpu_disp0_lvds0_ch1: endpoint@1 {
+				remote-endpoint = <&ldb1_ch1>;
 			};
 
 			dpu_disp0_mipi_dsi: endpoint@2 {
@@ -130,9 +132,11 @@ dc_subsys: bus@56000000 {
 			reg = <1>;
 
 			dpu_disp1_lvds1_ch0: endpoint@0 {
+				remote-endpoint = <&ldb2_ch0>;
 			};
 
 			dpu_disp1_lvds1_ch1: endpoint@1 {
+				remote-endpoint = <&ldb2_ch1>;
 			};
 
 			dpu_disp1_mipi_dsi: endpoint@2 {
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi
new file mode 100644
index 000000000000..52e85cd86b18
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+lvds_subsys: bus@56220000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x56220000 0x0 0x56220000 0x30000>;
+
+	irqsteer_mipi_lvds0: irqsteer@56220000 {
+		compatible = "fsl,imx-irqsteer";
+		reg = <0x56220000 0x1000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+		clocks = <&lvds_lpcg1 IMX_MIPI0_LPCG_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_MIPI_0>;
+	};
+
+	lvds_region1: lvds_region@56220000 {
+		compatible = "syscon";
+		reg = <0x56220000 0x10000>;
+	};
+
+	ldb1_phy: ldb_phy@56221000 {
+		compatible = "mixel,lvds-combo-phy";
+		reg = <0x56221000 0x100>, <0x56228000 0x1000>;
+		#phy-cells = <0>;
+		clocks = <&clk IMX_LVDS0_PHY_CLK>;
+		clock-names = "phy";
+		power-domains = <&pd IMX_SC_R_LVDS_0>;
+		status = "disabled";
+	};
+
+	ldb1: ldb@562210e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qxp-ldb";
+		clocks = <&clk IMX_LVDS0_PIXEL_CLK>,
+			 <&clk IMX_LVDS0_BYPASS_CLK>;
+		clock-names = "pixel", "bypass";
+		power-domains = <&pd IMX_SC_R_LVDS_0>;
+		gpr = <&lvds_region1>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb1_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_ch0: endpoint {
+					remote-endpoint = <&dpu_disp0_lvds0_ch0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb1_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_ch1: endpoint {
+					remote-endpoint = <&dpu_disp0_lvds0_ch1>;
+				};
+			};
+		};
+	};
+
+	lvds_lpcg1: clock-controller@56223000 {
+		compatible = "fsl,imx8qxp-lpcg-mipi0";
+		reg = <0x56223000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	i2c0_mipi_lvds0: i2c@56226000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x56226000 0x4000>;
+		interrupts = <8>;
+		interrupt-parent = <&irqsteer_mipi_lvds0>;
+		clocks = <&lvds_lpcg1 IMX_MIPI0_LPCG_I2C0_CLK>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_MIPI0_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+		status = "disabled";
+	};
+
+	irqsteer_mipi_lvds1: irqsteer@56240000 {
+		compatible = "fsl,imx-irqsteer";
+		reg = <0x56240000 0x1000>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+		clocks = <&lvds_lpcg2 IMX_MIPI1_LPCG_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_MIPI_1>;
+	};
+
+	lvds_region2: lvds_region@56240000 {
+		compatible = "syscon";
+		reg = <0x56240000 0x10000>;
+	};
+
+	ldb2_phy: ldb_phy@56241000 {
+		compatible = "mixel,lvds-combo-phy";
+		reg = <0x56241000 0x100>, <0x56248000 0x1000>;
+		#phy-cells = <0>;
+		clocks = <&clk IMX_LVDS1_PHY_CLK>;
+		clock-names = "phy";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+		status = "disabled";
+	};
+
+	ldb2: ldb@562410e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qxp-ldb";
+		clocks = <&clk IMX_LVDS1_PIXEL_CLK>,
+			 <&clk IMX_LVDS1_BYPASS_CLK>;
+		clock-names = "pixel", "bypass";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+		gpr = <&lvds_region2>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb2_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_ch0: endpoint {
+					remote-endpoint = <&dpu_disp1_lvds1_ch0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb2_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_ch1: endpoint {
+					remote-endpoint = <&dpu_disp1_lvds1_ch1>;
+				};
+			};
+		};
+	};
+
+	lvds_lpcg2: clock-controller@56243000 {
+		compatible = "fsl,imx8qxp-lpcg-mipi1";
+		reg = <0x56243000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	i2c0_mipi_lvds1: i2c@56246000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x56246000 0x4000>;
+		interrupts = <8>;
+		interrupt-parent = <&irqsteer_mipi_lvds1>;
+		clocks = <&lvds_lpcg2 IMX_MIPI1_LPCG_I2C0_CLK>;
+		clock-names = "per";
+		assigned-clocks = <&clk IMX_MIPI1_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 20434dcf9433..aed217e80799 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -27,6 +27,8 @@
 		gpio6 = &lsio_gpio6;
 		gpio7 = &lsio_gpio7;
 		dpu0 = &dpu1;
+		ldb0 = &ldb1;
+		ldb1 = &ldb2;
 		mmc0 = &usdhc1;
 		mmc1 = &usdhc2;
 		mmc2 = &usdhc3;
@@ -322,6 +324,7 @@
 	/* sorted in register address */
 	#include "imx8-ss-vpu.dtsi"
 	#include "imx8-ss-dc.dtsi"
+	#include "imx8-ss-lvds.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-ddr.dtsi"