diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-08-06 10:30:21 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:34 +0800 |
| commit | e419cb88c124a767edd0fb2cdb925c35810afa11 (patch) | |
| tree | b2f5d1d5df4cb913cd8316323707809c6a4cdf86 /arch | |
| parent | 99a1f25896761ff46a716daf6773629afa610293 (diff) | |
arm64: imx8qm.dtsi: Add DC0/1 subsystem support
This patch adds DC0/1 subsystem support for i.MX8qm.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi | 64 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 5 |
2 files changed, 69 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi new file mode 100644 index 000000000000..172f7127fdca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +&dpu1 { + compatible = "fsl,imx8qm-dpu"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + + dpu1_disp0: port@0 { + reg = <0>; + }; + + dpu1_disp1: port@1 { + reg = <1>; + + dpu1_disp1_ldb1_ch0: endpoint@0 { + }; + + dpu1_disp1_ldb1_ch1: endpoint@1 { + }; + }; +}; + +&dpu2 { + compatible = "fsl,imx8qm-dpu"; + clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_1>, + <&pd IMX_SC_R_DC_1_PLL_0>, + <&pd IMX_SC_R_DC_1_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + status = "disabled"; + + dpu2_disp0: port@0 { + reg = <0>; + }; + + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_ldb2_ch0: endpoint@0 { + }; + + dpu2_disp1_ldb2_ch1: endpoint@1 { + }; + }; +}; + +/ { + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 4cca61ef9d17..f10006f082e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -39,6 +39,8 @@ can0 = &flexcan1; can1 = &flexcan2; can2 = &flexcan3; + dpu0 = &dpu1; + dpu1 = &dpu2; }; cpus { @@ -391,6 +393,8 @@ #include "imx8-ss-lsio.dtsi" #include "imx8-ss-hsio.dtsi" #include "imx8-ss-img.dtsi" + #include "imx8-ss-dc0.dtsi" + #include "imx8-ss-dc1.dtsi" }; #include "imx8qm-ss-audio.dtsi" @@ -398,3 +402,4 @@ #include "imx8qm-ss-conn.dtsi" #include "imx8qm-ss-lsio.dtsi" #include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-dc.dtsi" |