mx6_oc: initial addition of board files

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

7 files changed, 1740 insertions, 0 deletions

diff --git a/arch/arm/configs/oc_defconfig b/arch/arm/configs/oc_defconfig
new file mode 100644
index 000000000000..c0837ed39ddb
--- /dev/null
+++ b/arch/arm/configs/oc_defconfig
@@ -0,0 +1,270 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_MX6=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_MACH_MX6_OC=y
+CONFIG_IMX_PCIE=y
+CONFIG_USB_EHCI_ARC_H1=y
+CONFIG_USB_FSL_ARC_OTG=y
+CONFIG_MXC_PWM=y
+CONFIG_MXC_REBOOT_MFGMODE=y
+CONFIG_CLK_DEBUG=y
+CONFIG_DMA_ZONE_SIZE=184
+# CONFIG_SWP_EMULATE is not set
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_COMPACTION=y
+CONFIG_KSM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_IMX=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_APM_EMULATION=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_LLC2=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_MULTIQ=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_CFG80211=m
+# CONFIG_CFG80211_WEXT is not set
+CONFIG_LIB80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_MISC_DEVICES=y
+CONFIG_MXS_PERFMON=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_MII=y
+CONFIG_MICREL_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_FEC_NAPI=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_BCMDHD=m
+CONFIG_INPUT_POLLDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_TSC2004=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_FSL_OTP=y
+CONFIG_HW_RANDOM=y
+CONFIG_MXS_VIIM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_MAX17135=y
+CONFIG_SENSORS_MAG3110=y
+# CONFIG_MXC_MMA8450 is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_WM8994=y
+CONFIG_MFD_PFUZE=y
+CONFIG_MFD_MAX17135=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_MAX17135=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_VIDEO_MXC_CAMERA=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_HIDRAW=y
+CONFIG_HID_QUANTA=y
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG_WHITELIST is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ARC=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_QUALCOMM=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MXC_OTG=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_ISL1208=y
+CONFIG_DMADEVICES=y
+CONFIG_MXC_PXP_V2=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXC_IPU=y
+# CONFIG_MXC_HMP4E is not set
+# CONFIG_MXC_HWEVENT is not set
+CONFIG_MXC_ASRC=y
+CONFIG_MXC_GPU_VIV=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC7=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index 5c267948b5d8..0597a935d9eb 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -180,6 +180,43 @@ config MACH_MX6Q_SABRELITE
 	  Include support for i.MX 6Quad SABRE Lite platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_MX6_OC
+	bool "Support i.MX 6Quad OC platform"
+	select ARCH_MX6Q
+	select SOC_IMX6Q
+	select IMX_HAVE_PLATFORM_IMX_UART
+	select IMX_HAVE_PLATFORM_DMA
+	select IMX_HAVE_PLATFORM_FEC
+	select IMX_HAVE_PLATFORM_GPMI_NFC
+	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+	select IMX_HAVE_PLATFORM_SPI_IMX
+	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_VIV_GPU
+	select IMX_HAVE_PLATFORM_IMX_VPU
+	select IMX_HAVE_PLATFORM_IMX_SSI
+	select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL
+	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+	select IMX_HAVE_PLATFORM_MXC_EHCI
+	select IMX_HAVE_PLATFORM_FSL_OTG
+	select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP
+	select IMX_HAVE_PLATFORM_AHCI
+	select IMX_HAVE_PLATFORM_IMX_OCOTP
+	select IMX_HAVE_PLATFORM_IMX_VIIM
+	select IMX_HAVE_PLATFORM_IMX2_WDT
+	select IMX_HAVE_PLATFORM_IMX_SNVS_RTC
+	select IMX_HAVE_PLATFORM_IMX_PM
+	select IMX_HAVE_PLATFORM_MXC_HDMI
+	select IMX_HAVE_PLATFORM_IMX_ASRC
+	select IMX_HAVE_PLATFORM_FLEXCAN
+	select IMX_HAVE_PLATFORM_IMX_CAAM
+	select IMX_HAVE_PLATFORM_IMX_DVFS
+	select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2
+	select IMX_HAVE_PLATFORM_IMX_PCIE
+	select IMX_HAVE_PLATFORM_PERFMON
+	help
+	  Include support for i.MX 6Quad OC platform. This includes specific
+	  configurations for the board and its peripherals.
+
 config MACH_MX6Q_SABRESD
 	bool "Support i.MX 6Quad SABRESD platform"
 	select ARCH_MX6Q
diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile
index 1899641220f1..1bc5a34f09db 100644
--- a/arch/arm/mach-mx6/Makefile
+++ b/arch/arm/mach-mx6/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o
 obj-$(CONFIG_MACH_MX6_NITROGEN6X) += board-mx6_nitrogen6x.o
+obj-$(CONFIG_MACH_MX6_OC) += board-mx6_oc.o
 obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o
 obj-$(CONFIG_MACH_MX6Q_HDMIDONGLE) += board-mx6q_hdmidongle.o
diff --git a/arch/arm/mach-mx6/board-mx6_oc.c b/arch/arm/mach-mx6/board-mx6_oc.c
new file mode 100644
index 000000000000..de3811e70ead
--- /dev/null
+++ b/arch/arm/mach-mx6/board-mx6_oc.c
@@ -0,0 +1,1166 @@
+/*
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/ata.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/pwm.h>
+#include <linux/pwm_backlight.h>
+#include <linux/fec.h>
+#include <linux/memblock.h>
+#include <linux/gpio.h>
+#include <linux/gpio-i2cmux.h>
+#include <linux/etherdevice.h>
+#include <linux/regulator/anatop-regulator.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/memory.h>
+#include <mach/iomux-mx6q.h>
+#include <mach/iomux-mx6dl.h>
+#include <mach/imx-uart.h>
+#include <mach/viv_gpu.h>
+#include <mach/ahci_sata.h>
+#include <mach/ipu-v3.h>
+#include <mach/mxc_hdmi.h>
+#include <mach/mxc_asrc.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/wl12xx.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "usb.h"
+#include "devices-imx6q.h"
+#include "crm_regs.h"
+#include "cpu_op-mx6.h"
+
+#define MX6_OC_AUDIO_MUTE		IMX_GPIO_NR(5, 2)	/* EIM_A25 - active low */
+
+#define MX6_OC_CAMERA_I2C_EN		IMX_GPIO_NR(3, 20)	/* EIM_D20 - active high */
+#define MX6_OC_CAMERA_PWDN		IMX_GPIO_NR(1, 16)	/* SD1_DAT0 - active high */
+#define MX6_OC_CAMERA_GP		IMX_GPIO_NR(1, 6)	/* GPIO_6  */
+#define MX6_OC_CAMERA_RESET		IMX_GPIO_NR(1, 8)	/* GPIO_8 - active low */
+
+#define MX6_OC_DISP_I2C_EN		IMX_GPIO_NR(2, 17)	/* EIM_A21 - active high */
+#define MX6_OC_DISP_BACKLIGHT_EN	IMX_GPIO_NR(1, 17)	/* SD1_DAT1 - active high */
+#define MX6_OC_DISP_BACKLIGHT_12V_EN	IMX_GPIO_NR(4, 5)	/* GPIO_19 - active high */
+
+#define MX6_OC_ENET_PHY_RESET		IMX_GPIO_NR(1, 27)	/* ENET_RXD0 - active low */
+#define MX6_OC_ENET_PHY_IRQ		IMX_GPIO_NR(1, 28)	/* ENET_TX_EN - active low */
+
+#define MX6_OC_PCIE_RESET		IMX_GPIO_NR(3, 22)	/* EIM_CS0 - active low */
+
+#define MX6_OC_RTC_I2C_EN		IMX_GPIO_NR(2, 23)	/* EIM_CS0 - active high */
+#define MX6_OC_RTC_IRQ			IMX_GPIO_NR(2, 24)	/* EIM_CS1 - active low */
+
+#define MX6_OC_ST_EMMC_RESET		IMX_GPIO_NR(2, 5)	/* NANDF_D5 - active low */
+#define MX6_OC_ST_SD3_CD		IMX_GPIO_NR(7, 0)	/* SD3_DAT5 - active low */
+#define MX6_OC_ST_ECSPI1_CS1		IMX_GPIO_NR(3, 19)	/* EIM_D19 - active low */
+
+#define MX6_OC_TOUCH_RESET		IMX_GPIO_NR(1, 4)	/* GPIO_4 - active low */
+#define MX6_OC_TOUCH_IRQ		IMX_GPIO_NR(1, 9)	/* GPIO_9 - active low */
+
+#define MX6_OC_USB_HUB_RESET		IMX_GPIO_NR(7, 12)	/* GPIO_17 - active low */
+
+#define MX6_OC_WL_BT_RESET		IMX_GPIO_NR(6, 8)	/* NANDF_ALE - active low */
+#define MX6_OC_WL_BT_REG_EN		IMX_GPIO_NR(6, 15)	/* NANDF_CS2 - active high */
+#define MX6_OC_WL_BT_WAKE_IRQ		IMX_GPIO_NR(6, 16)	/* NANDF_CS3 - active low */
+
+#define MX6_OC_WL_EN			IMX_GPIO_NR(6, 7)	/* NANDF_CLE - active high */
+#define MX6_OC_WL_CLK_REQ_IRQ		IMX_GPIO_NR(6, 9)	/* NANDF_WP_B - active low */
+#define MX6_OC_WL_WAKE_IRQ		IMX_GPIO_NR(6, 14)	/* NANDF_CS1 - active low */
+
+
+#include "pads-mx6_oc.h"
+#define FOR_DL_SOLO
+#include "pads-mx6_oc.h"
+
+void __init early_console_setup(unsigned long base, struct clk *clk);
+static struct clk *sata_clk;
+
+extern char *gp_reg_id;
+extern char *soc_reg_id;
+extern char *pu_reg_id;
+
+extern struct regulator *(*get_cpu_regulator)(void);
+extern void (*put_cpu_regulator)(void);
+
+#define IOMUX_SETUP(pad_list)	mxc_iomux_v3_setup_pads(mx6q_##pad_list, \
+		mx6dl_solo_##pad_list)
+
+int mxc_iomux_v3_setup_pads(iomux_v3_cfg_t *mx6q_pad_list,
+		iomux_v3_cfg_t *mx6dl_solo_pad_list)
+{
+        iomux_v3_cfg_t *p = cpu_is_mx6q() ? mx6q_pad_list : mx6dl_solo_pad_list;
+        int ret;
+
+        while (*p) {
+                ret = mxc_iomux_v3_setup_pad(*p);
+                if (ret)
+                        return ret;
+                p++;
+        }
+        return 0;
+}
+
+#define GPIOF_HIGH	GPIOF_OUT_INIT_HIGH
+struct gpio mx6_oc_init_gpios[] __initdata = {
+	{.label = "audio_mute",		.gpio = MX6_OC_AUDIO_MUTE,	.flags = 0},		/* GPIO5[2]: EIM_A25 - active low */
+
+//	{.label = "camera_i2c_en",	.gpio = MX6_OC_CAMERA_I2C_EN,	.flags = 0},		/* GPIO3[20]: EIM_D20 - active high */
+	{.label = "camera_pwdn",	.gpio = MX6_OC_CAMERA_PWDN,	.flags = GPIOF_HIGH},	/* GPIO1[16]: SD1_DAT0 - active high */
+	{.label = "camera_gp",		.gpio = MX6_OC_CAMERA_GP,	.flags = 0},		/* GPIO1[6]: GPIO_6  */
+	{.label = "camera_reset",	.gpio = MX6_OC_CAMERA_RESET,	.flags = 0},		/* GPIO1[8]: GPIO_8 - active low */
+
+//	{.label = "edid_i2c_en",	.gpio = MX6_OC_DISP_I2C_EN,	.flags = 0},		/* GPIO2[17]: EIM_A21 - active high */
+	{.label = "backlight_en",	.gpio = MX6_OC_DISP_BACKLIGHT_EN, .flags = 0},		/* GPIO1[17]: SD1_DAT1 - active high */
+	{.label = "backlight_12V_en",	.gpio = MX6_OC_DISP_BACKLIGHT_12V_EN, .flags = 0},	/* GPIO4[5]: GPIO_19 - active high */
+
+	{.label = "phy_reset",		.gpio = MX6_OC_ENET_PHY_RESET,	.flags = GPIOF_HIGH},	/* GPIO1[27]: ENET_RXD0 - active low */
+//	{.label = "phy_irq",		.gpio = MX6_OC_ENET_PHY_IRQ,	.flags = GPIOF_DIR_IN},	/* GPIO1[28]: ENET_TX_EN - active low */
+
+//	{.label = "pcie_reset",		.gpio = MX6_OC_PCIE_RESET,	.flags = 0},		/* GPIO3[22]: EIM_D22 - active low */
+
+//	{.label = "rtc_i2c_en",		.gpio = MX6_OC_RTC_I2C_EN,	.flags = 0},		/* GPIO2[23]: EIM_CS0 - active high */
+	{.label = "rtc_irq",		.gpio = MX6_OC_RTC_IRQ,		.flags = GPIOF_DIR_IN},	/* GPIO2[24]:* EIM_CS1 - active low */
+
+	{.label = "emmc_reset",		.gpio = MX6_OC_ST_EMMC_RESET,	.flags = GPIOF_HIGH},	/* GPIO2[5]: NANDF_D5 - active low */
+	{.label = "sd3_cd",		.gpio = MX6_OC_ST_SD3_CD,	.flags = GPIOF_DIR_IN},	/* GPIO7[0]: SD3_DAT5 - active low */
+//	{.label = "spi_no_cs1",		.gpio = MX6_OC_ST_ECSPI1_CS1,	.flags = GPIOF_HIGH},	/* GPIO3[19]: EIM_D19 - active low */
+
+	{.label = "touch_reset",	.gpio = MX6_OC_TOUCH_RESET,	.flags = GPIOF_HIGH},		/* GPIO1[4]: GPIO_4 - active low */
+	{.label = "touch_irq",		.gpio = MX6_OC_TOUCH_IRQ,	.flags = GPIOF_DIR_IN},	/* GPIO1[9]: GPIO_9 - active low */
+
+	{.label = "usb_hub_reset",	.gpio = MX6_OC_USB_HUB_RESET,	.flags = 0},		/* GPIO7[12]: GPIO_17 - active low */
+
+	{.label = "bt_reset",		.gpio = MX6_OC_WL_BT_RESET,	.flags = 0},		/* GPIO6[8]: NANDF_ALE - active low */
+	{.label = "bt_reg_en",		.gpio = MX6_OC_WL_BT_REG_EN,	.flags = 0},		/* GPIO6[15]: NANDF_CS2 - active high */
+	{.label = "bt_wake_irq",	.gpio = MX6_OC_WL_BT_WAKE_IRQ,	.flags = GPIOF_DIR_IN},	/* GPIO6[16]: NANDF_CS3 - active low */
+
+	{.label = "wl_en",		.gpio = MX6_OC_WL_EN,		.flags = 0},		/* GPIO6[7]: NANDF_CLE - active high */
+	{.label = "wl_clk_req_irq",	.gpio = MX6_OC_WL_CLK_REQ_IRQ,	.flags = GPIOF_DIR_IN},	/* GPIO6[9]: NANDF_WP_B - active low */
+	{.label = "wl_wake_irq",	.gpio = MX6_OC_WL_WAKE_IRQ,	.flags = GPIOF_DIR_IN},	/* GPIO6[14]: NANDF_CS1 - active low */
+};
+
+
+enum sd_pad_mode {
+	SD_PAD_MODE_LOW_SPEED,
+	SD_PAD_MODE_MED_SPEED,
+	SD_PAD_MODE_HIGH_SPEED,
+};
+
+static int plt_sd_pad_change(unsigned int index, int clock)
+{
+	/* LOW speed is the default state of SD pads */
+	static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
+	int i = (index - 1) * SD_SPEED_CNT;
+
+	if ((index < 1) || (index > 3)) {
+		printk(KERN_ERR "no such SD host controller index %d\n", index);
+		return -EINVAL;
+	}
+
+	if (clock > 100000000) {
+		if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
+			return 0;
+		pad_mode = SD_PAD_MODE_HIGH_SPEED;
+		i += _200MHZ;
+	} else if (clock > 52000000) {
+		if (pad_mode == SD_PAD_MODE_MED_SPEED)
+			return 0;
+		pad_mode = SD_PAD_MODE_MED_SPEED;
+		i += _100MHZ;
+	} else {
+		if (pad_mode == SD_PAD_MODE_LOW_SPEED)
+			return 0;
+		pad_mode = SD_PAD_MODE_LOW_SPEED;
+		i += _50MHZ;
+	}
+	return IOMUX_SETUP(sd_pads[i]);
+}
+
+/* Broadcom wifi */
+static struct esdhc_platform_data mx6_oc_sd2_data = {
+	.always_present = 1,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.keep_power_at_suspend = 0,
+	.caps = MMC_CAP_POWER_OFF_CARD,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+/* SD card */
+static struct esdhc_platform_data mx6_oc_sd3_data = {
+	.cd_gpio = MX6_OC_ST_SD3_CD,
+	.wp_gpio = -1,
+	.keep_power_at_suspend = 1,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+/* EMMC */
+static const struct esdhc_platform_data mx6_oc_sd4_data __initconst = {
+	.always_present = 1,
+	.support_18v = 1,
+	.support_8bit = 1,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.keep_power_at_suspend = 1,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
+static const struct anatop_thermal_platform_data
+	mx6_oc_anatop_thermal_data __initconst = {
+		.name = "anatop_thermal",
+};
+
+static const struct imxuart_platform_data mx6_arm2_uart2_data __initconst = {
+	.flags      = IMXUART_HAVE_RTSCTS | IMXUART_SDMA,
+	.dma_req_rx = MX6Q_DMA_REQ_UART3_RX,
+	.dma_req_tx = MX6Q_DMA_REQ_UART3_TX,
+};
+
+static int mx6_oc_fec_phy_init(struct phy_device *phydev)
+{
+	/* prefer master mode */
+	phy_write(phydev, 0x9, 0x1f00);
+
+	/* min rx data delay */
+	phy_write(phydev, 0x0b, 0x8105);
+	phy_write(phydev, 0x0c, 0x0000);
+
+	/* min tx data delay */
+	phy_write(phydev, 0x0b, 0x8106);
+	phy_write(phydev, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(phydev, 0x0b, 0x8104);
+	phy_write(phydev, 0x0c, 0xf0f0);
+	phy_write(phydev, 0x0b, 0x104);
+	return 0;
+}
+
+static struct fec_platform_data fec_data __initdata = {
+	.init = mx6_oc_fec_phy_init,
+	.phy = PHY_INTERFACE_MODE_RGMII,
+	.phy_irq = gpio_to_irq(MX6_OC_ENET_PHY_IRQ)
+};
+
+static int mx6_oc_spi_cs[] = {
+	MX6_OC_ST_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx6_oc_spi_data __initconst = {
+	.chipselect     = mx6_oc_spi_cs,
+	.num_chipselect = ARRAY_SIZE(mx6_oc_spi_cs),
+};
+
+#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+static struct mtd_partition imx6_oc_spi_nor_partitions[] = {
+	{
+	 .name = "bootloader",
+	 .offset = 0,
+	 .size = 768*1024,
+	},
+	{
+	 .name = "ubparams",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = 8*1024,
+	},
+	{
+	 .name = "unused",
+	 .offset = MTDPART_OFS_APPEND,
+	 .size = MTDPART_SIZ_FULL,
+	},
+};
+
+static struct flash_platform_data imx6_oc__spi_flash_data = {
+	.name = "m25p80",
+	.parts = imx6_oc_spi_nor_partitions,
+	.nr_parts = ARRAY_SIZE(imx6_oc_spi_nor_partitions),
+	.type = "sst25vf016b",
+};
+#endif
+
+static struct spi_board_info imx6_oc_spi_nor_device[] __initdata = {
+#if defined(CONFIG_MTD_M25P80)
+	{
+		.modalias = "m25p80",
+		.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
+		.bus_num = 0,
+		.chip_select = 0,
+		.platform_data = &imx6_oc__spi_flash_data,
+	},
+#endif
+};
+
+static void spi_device_init(void)
+{
+	spi_register_board_info(imx6_oc_spi_nor_device,
+				ARRAY_SIZE(imx6_oc_spi_nor_device));
+}
+
+static struct mxc_audio_platform_data mx6_oc_audio_data;
+
+static int mx6_oc_sgtl5000_init(void)
+{
+	struct clk *clko;
+	struct clk *new_parent;
+	int rate;
+
+	clko = clk_get(NULL, "clko_clk");
+	if (IS_ERR(clko)) {
+		pr_err("can't get CLKO clock.\n");
+		return PTR_ERR(clko);
+	}
+	new_parent = clk_get(NULL, "ahb");
+	if (!IS_ERR(new_parent)) {
+		clk_set_parent(clko, new_parent);
+		clk_put(new_parent);
+	}
+	rate = clk_round_rate(clko, 16000000);
+	if (rate < 8000000 || rate > 27000000) {
+		pr_err("Error:SGTL5000 mclk freq %d out of range!\n", rate);
+		clk_put(clko);
+		return -1;
+	}
+	pr_info("%s: rate=%d\n", __func__, rate);
+	mx6_oc_audio_data.sysclk = rate;
+	clk_set_rate(clko, rate);
+	clk_enable(clko);
+	return 0;
+}
+
+int mx6_oc_amp_enable(int enable)
+{
+	gpio_set_value(MX6_OC_AUDIO_MUTE, enable ? 1 : 0);
+	return 0;
+}
+
+static struct imx_ssi_platform_data mx6_oc_ssi_pdata = {
+	.flags = IMX_SSI_DMA | IMX_SSI_SYN,
+};
+
+static struct mxc_audio_platform_data mx6_oc_audio_data = {
+	.ssi_num = 1,
+	.src_port = 2,
+	.ext_port = 3,
+	.init = mx6_oc_sgtl5000_init,
+	.hp_gpio = -1,
+	.mic_gpio = -1,
+	.amp_enable = mx6_oc_amp_enable,
+};
+
+static struct platform_device mx6_oc_audio_device = {
+	.name = "imx-sgtl5000",
+};
+
+static struct imxi2c_platform_data mx6_oc_i2c_data = {
+	.bitrate = 100000,
+};
+
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("sgtl5000", 0x0a),
+	},
+};
+
+/*
+ **********************************************************************
+ */
+static struct tsc2007_platform_data tsc2007_info = {
+	.model			= 2004,
+	.x_plate_ohms		= 500,
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("tsc2004", 0x48),
+		.platform_data	= &tsc2007_info,
+		.irq = gpio_to_irq(MX6_OC_TOUCH_IRQ),
+	},
+};
+/*
+ **********************************************************************
+ */
+/* i2C bus has a switch */
+static const unsigned i2c0_gpiomux_gpios[] = {
+	MX6_OC_CAMERA_I2C_EN,	/* i2c3 */
+	MX6_OC_RTC_I2C_EN,	/* i2c4 */
+};
+
+static const unsigned i2c0_gpiomux_values[] = {
+	1, 2,
+};
+
+static struct gpio_i2cmux_platform_data i2c0_i2cmux_data = {
+	.parent		= 0,
+	.base_nr	= 3, /* optional */
+	.values		= i2c0_gpiomux_values,
+	.n_values	= ARRAY_SIZE(i2c0_gpiomux_values),
+	.gpios		= i2c0_gpiomux_gpios,
+	.n_gpios	= ARRAY_SIZE(i2c0_gpiomux_gpios),
+	.idle		= 0,
+};
+
+static struct platform_device i2c0_i2cmux = {
+        .name           = "gpio-i2cmux",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &i2c0_i2cmux_data,
+        },
+};
+
+/*
+ **********************************************************************
+ */
+/* i2C bus has a switch */
+static const unsigned i2c2_gpiomux_gpios[] = {
+	MX6_OC_DISP_I2C_EN,	/* i2c5 - edid */
+};
+
+static const unsigned i2c2_gpiomux_values[] = {
+	1,
+};
+
+static struct gpio_i2cmux_platform_data i2c2_i2cmux_data = {
+	.parent		= 2,
+	.base_nr	= 5, /* optional */
+	.values		= i2c2_gpiomux_values,
+	.n_values	= ARRAY_SIZE(i2c2_gpiomux_values),
+	.gpios		= i2c2_gpiomux_gpios,
+	.n_gpios	= ARRAY_SIZE(i2c2_gpiomux_gpios),
+	.idle		= 0,
+};
+
+static struct platform_device i2c2_i2cmux = {
+        .name           = "gpio-i2cmux",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &i2c2_i2cmux_data,
+        },
+};
+
+/*
+ **********************************************************************
+ */
+static void camera_reset(int power_gp, int reset_gp, int reset_gp2)
+{
+	pr_info("%s: power_gp=0x%x, reset_gp=0x%x reset_gp2=0x%x\n",
+			__func__, power_gp, reset_gp, reset_gp2);
+	/* Camera power down */
+	gpio_direction_output(power_gp, 1);
+	/* Camera reset */
+	gpio_direction_output(reset_gp, 0);
+	if (reset_gp2 >= 0)
+		gpio_direction_output(reset_gp2, 0);
+	msleep(1);
+	gpio_set_value(power_gp, 0);
+	msleep(1);
+	gpio_set_value(reset_gp, 1);
+	if (reset_gp2 >= 0)
+		gpio_set_value(reset_gp2, 1);
+}
+
+
+/*
+ * OV5642 Camera
+ */
+static void mx6_csi0_io_init(void)
+{
+	camera_reset(MX6_OC_CAMERA_PWDN, MX6_OC_CAMERA_RESET,
+			MX6_OC_CAMERA_GP);
+	/* For MX6Q GPR1 bit19 and bit20 meaning:
+	 * Bit19:       0 - Enable mipi to IPU1 CSI0
+	 *                      virtual channel is fixed to 0
+	 *              1 - Enable parallel interface to IPU1 CSI0
+	 * Bit20:       0 - Enable mipi to IPU2 CSI1
+	 *                      virtual channel is fixed to 3
+	 *              1 - Enable parallel interface to IPU2 CSI1
+	 * IPU1 CSI1 directly connect to mipi csi2,
+	 *      virtual channel is fixed to 1
+	 * IPU2 CSI0 directly connect to mipi csi2,
+	 *      virtual channel is fixed to 2
+	 */
+	if (cpu_is_mx6q())
+		mxc_iomux_set_gpr_register(1, 19, 1, 1);
+	else
+		mxc_iomux_set_gpr_register(13, 0, 3, 4);
+}
+
+static void mx6_csi0_powerdown(int powerdown)
+{
+	pr_info("%s: powerdown=%d, power_gp=0x%x\n",
+			__func__, powerdown, MX6_OC_CAMERA_PWDN);
+	gpio_set_value(MX6_OC_CAMERA_PWDN, powerdown ? 1 : 0);
+	msleep(2);
+}
+
+static struct fsl_mxc_camera_platform_data camera_data = {
+	.mclk = 24000000,
+	.mclk_source = 0,
+	.csi = 0,
+	.io_init = mx6_csi0_io_init,
+	.pwdn = mx6_csi0_powerdown,
+};
+
+static struct i2c_board_info mxc_i2c3_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("ov5642", 0x3c),
+		.platform_data = (void *)&camera_data,
+	},
+};
+
+/*
+ **********************************************************************
+ */
+static struct i2c_board_info mxc_i2c4_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("isl1208", 0x6f),	/* Real time clock */
+	},
+};
+
+static struct i2c_board_info mxc_i2c5_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
+	},
+};
+/*
+ **********************************************************************
+ */
+
+static void imx6_oc_usbotg_vbus(bool on)
+{
+}
+
+static void __init imx6_oc_init_usb(void)
+{
+	imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
+	/* disable external charger detect,
+	 * or it will affect signal quality at dp .
+	 */
+	mxc_iomux_set_gpr_register(1, 13, 1, 1);
+
+	mx6_set_otghost_vbus_func(imx6_oc_usbotg_vbus);
+}
+
+/* HW Initialization, if return 0, initialization is successful. */
+static int mx6_oc_sata_init(struct device *dev, void __iomem *addr)
+{
+	u32 tmpdata;
+	int ret = 0;
+	struct clk *clk;
+
+	sata_clk = clk_get(dev, "imx_sata_clk");
+	if (IS_ERR(sata_clk)) {
+		dev_err(dev, "no sata clock.\n");
+		return PTR_ERR(sata_clk);
+	}
+	ret = clk_enable(sata_clk);
+	if (ret) {
+		dev_err(dev, "can't enable sata clock.\n");
+		goto put_sata_clk;
+	}
+
+	/* Set PHY Paremeters, two steps to configure the GPR13,
+	 * one write for rest of parameters, mask of first write is 0x07FFFFFD,
+	 * and the other one write for setting the mpll_clk_off_b
+	 *.rx_eq_val_0(iomuxc_gpr13[26:24]),
+	 *.los_lvl(iomuxc_gpr13[23:19]),
+	 *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
+	 *.sata_speed(iomuxc_gpr13[15]),
+	 *.mpll_ss_en(iomuxc_gpr13[14]),
+	 *.tx_atten_0(iomuxc_gpr13[13:11]),
+	 *.tx_boost_0(iomuxc_gpr13[10:7]),
+	 *.tx_lvl(iomuxc_gpr13[6:2]),
+	 *.mpll_ck_off(iomuxc_gpr13[1]),
+	 *.tx_edgerate_0(iomuxc_gpr13[0]),
+	 */
+	tmpdata = readl(IOMUXC_GPR13);
+	writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
+
+	/* enable SATA_PHY PLL */
+	tmpdata = readl(IOMUXC_GPR13);
+	writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
+
+	/* Get the AHB clock rate, and configure the TIMER1MS reg later */
+	clk = clk_get(NULL, "ahb");
+	if (IS_ERR(clk)) {
+		dev_err(dev, "no ahb clock.\n");
+		ret = PTR_ERR(clk);
+		goto release_sata_clk;
+	}
+	tmpdata = clk_get_rate(clk) / 1000;
+	clk_put(clk);
+
+	ret = sata_init(addr, tmpdata);
+	if (ret == 0)
+		return ret;
+
+release_sata_clk:
+	clk_disable(sata_clk);
+put_sata_clk:
+	clk_put(sata_clk);
+
+	return ret;
+}
+
+static void mx6_oc_sata_exit(struct device *dev)
+{
+	clk_disable(sata_clk);
+	clk_put(sata_clk);
+}
+
+static struct ahci_platform_data mx6_oc_sata_data = {
+	.init = mx6_oc_sata_init,
+	.exit = mx6_oc_sata_exit,
+};
+
+static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = {
+	.reserved_mem_size = SZ_128M,
+};
+
+static struct imx_asrc_platform_data imx_asrc_data = {
+	.channel_bits = 4,
+	.clk_map_ver = 2,
+};
+
+static struct ipuv3_fb_platform_data oc_fb_data[] = {
+	{ /*fb0*/
+	.disp_dev = "ldb",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
+	.mode_str = "LDB-VGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	}, {
+	.disp_dev = "lcd",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB565,
+	.mode_str = "CLAA-WVGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	}, {
+	.disp_dev = "ldb",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
+	.mode_str = "LDB-SVGA",
+	.default_bpp = 16,
+	.int_clk = false,
+	},
+};
+
+static void hdmi_init(int ipu_id, int disp_id)
+{
+	int hdmi_mux_setting;
+
+	if ((ipu_id > 1) || (ipu_id < 0)) {
+		pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
+		ipu_id = 0;
+	}
+
+	if ((disp_id > 1) || (disp_id < 0)) {
+		pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
+		disp_id = 0;
+	}
+
+	/* Configure the connection between IPU1/2 and HDMI */
+	hdmi_mux_setting = 2*ipu_id + disp_id;
+
+	/* GPR3, bits 2-3 = HDMI_MUX_CTL */
+	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
+
+	/* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */
+	if ((mx6q_revision() > IMX_CHIP_REVISION_1_1))
+		mxc_iomux_set_gpr_register(0, 0, 1, 1);
+}
+
+static void hdmi_enable_ddc_pin(void)
+{
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+}
+
+static struct fsl_mxc_hdmi_platform_data hdmi_data = {
+	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
+};
+
+static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
+	.ipu_id = 0,
+	.disp_id = 1,
+};
+
+static struct fsl_mxc_ldb_platform_data ldb_data = {
+	.ipu_id = 1,
+	.disp_id = 0,
+	.ext_ref = 1,
+	.mode = LDB_SEP0,
+	.sec_ipu_id = 1,
+	.sec_disp_id = 1,
+};
+
+static struct imx_ipuv3_platform_data ipu_data[] = {
+	{
+	.rev = 4,
+	.csi_clk[0] = "clko2_clk",
+	}, {
+	.rev = 4,
+	.csi_clk[0] = "clko2_clk",
+	},
+};
+
+static struct fsl_mxc_capture_platform_data capture_data = {
+	.csi = 0,
+	.ipu = 0,
+	.mclk_source = 0,
+	.is_mipi = 0,
+};
+
+
+static void oc_suspend_enter(void)
+{
+	/* suspend preparation */
+}
+
+static void oc_suspend_exit(void)
+{
+	/* resume restore */
+}
+static const struct pm_platform_data mx6_oc_pm_data __initconst = {
+	.name = "imx_pm",
+	.suspend_enter = oc_suspend_enter,
+	.suspend_exit = oc_suspend_exit,
+};
+
+static struct regulator_consumer_supply mx6_oc_vwifi_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+};
+
+static struct regulator_init_data mx6_oc_vwifi_init = {
+	.constraints            = {
+		.name           = "VDD_1.8V",
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(mx6_oc_vwifi_consumers),
+	.consumer_supplies = mx6_oc_vwifi_consumers,
+};
+
+static struct fixed_voltage_config mx6_oc_vwifi_reg_config = {
+	.supply_name		= "vwifi",
+	.microvolts		= 1800000, /* 1.80V */
+	.gpio			= MX6_OC_WL_EN,
+	.startup_delay		= 70000, /* 70ms */
+	.enable_high		= 1,
+	.enabled_at_boot	= 0,
+	.init_data		= &mx6_oc_vwifi_init,
+};
+
+static struct platform_device mx6_oc_vwifi_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 4,
+	.dev	= {
+		.platform_data = &mx6_oc_vwifi_reg_config,
+	},
+};
+
+static struct regulator_consumer_supply oc_vmmc_consumers[] = {
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
+	REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
+};
+
+static struct regulator_init_data oc_vmmc_init = {
+	.num_consumer_supplies = ARRAY_SIZE(oc_vmmc_consumers),
+	.consumer_supplies = oc_vmmc_consumers,
+};
+
+static struct fixed_voltage_config oc_vmmc_reg_config = {
+	.supply_name		= "vmmc",
+	.microvolts		= 3300000,
+	.gpio			= -1,
+	.init_data		= &oc_vmmc_init,
+};
+
+static struct platform_device oc_vmmc_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 3,
+	.dev	= {
+		.platform_data = &oc_vmmc_reg_config,
+	},
+};
+
+#ifdef CONFIG_SND_SOC_SGTL5000
+
+static struct regulator_consumer_supply sgtl5000_oc_consumer_vdda = {
+	.supply = "VDDA",
+	.dev_name = "0-000a",
+};
+
+static struct regulator_consumer_supply sgtl5000_oc_consumer_vddio = {
+	.supply = "VDDIO",
+	.dev_name = "0-000a",
+};
+
+static struct regulator_consumer_supply sgtl5000_oc_consumer_vddd = {
+	.supply = "VDDD",
+	.dev_name = "0-000a",
+};
+
+static struct regulator_init_data sgtl5000_oc_vdda_reg_initdata = {
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &sgtl5000_oc_consumer_vdda,
+};
+
+static struct regulator_init_data sgtl5000_oc_vddio_reg_initdata = {
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &sgtl5000_oc_consumer_vddio,
+};
+
+static struct regulator_init_data sgtl5000_oc_vddd_reg_initdata = {
+	.num_consumer_supplies = 1,
+	.consumer_supplies = &sgtl5000_oc_consumer_vddd,
+};
+
+static struct fixed_voltage_config sgtl5000_oc_vdda_reg_config = {
+	.supply_name		= "VDDA",
+	.microvolts		= 2500000,
+	.gpio			= -1,
+	.init_data		= &sgtl5000_oc_vdda_reg_initdata,
+};
+
+static struct fixed_voltage_config sgtl5000_oc_vddio_reg_config = {
+	.supply_name		= "VDDIO",
+	.microvolts		= 3300000,
+	.gpio			= -1,
+	.init_data		= &sgtl5000_oc_vddio_reg_initdata,
+};
+
+static struct fixed_voltage_config sgtl5000_oc_vddd_reg_config = {
+	.supply_name		= "VDDD",
+	.microvolts		= 3300000,
+	.gpio			= -1,
+	.init_data		= &sgtl5000_oc_vddd_reg_initdata,
+};
+
+static struct platform_device sgtl5000_oc_vdda_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 0,
+	.dev	= {
+		.platform_data = &sgtl5000_oc_vdda_reg_config,
+	},
+};
+
+static struct platform_device sgtl5000_oc_vddio_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 1,
+	.dev	= {
+		.platform_data = &sgtl5000_oc_vddio_reg_config,
+	},
+};
+
+static struct platform_device sgtl5000_oc_vddd_reg_devices = {
+	.name	= "reg-fixed-voltage",
+	.id	= 2,
+	.dev	= {
+		.platform_data = &sgtl5000_oc_vddd_reg_config,
+	},
+};
+
+#endif /* CONFIG_SND_SOC_SGTL5000 */
+
+static int imx6_init_audio(void)
+{
+	mxc_register_device(&mx6_oc_audio_device,
+			    &mx6_oc_audio_data);
+	imx6q_add_imx_ssi(1, &mx6_oc_ssi_pdata);
+#ifdef CONFIG_SND_SOC_SGTL5000
+	platform_device_register(&sgtl5000_oc_vdda_reg_devices);
+	platform_device_register(&sgtl5000_oc_vddio_reg_devices);
+	platform_device_register(&sgtl5000_oc_vddd_reg_devices);
+#endif
+	return 0;
+}
+
+int mx6_oc_bl_notify(struct device *dev, int brightness)
+{
+	pr_info("%s: brightness=%d\n", __func__, brightness);
+	gpio_set_value(MX6_OC_DISP_BACKLIGHT_12V_EN, brightness ? 1 : 0);
+	gpio_set_value(MX6_OC_DISP_BACKLIGHT_EN, brightness ? 1 : 0);
+	return brightness;
+}
+
+/* PWM4_PWMO: backlight control on LDB connector */
+static struct platform_pwm_backlight_data mx6_oc_pwm4_backlight_data = {
+	.pwm_id = 3,	/* pin SD1_CMD - PWM4 */
+	.max_brightness = 256,
+	.dft_brightness = 128,
+	.pwm_period_ns = 50000,
+	.notify = mx6_oc_bl_notify,
+};
+
+static struct mxc_dvfs_platform_data oc_dvfscore_data = {
+	.reg_id = "cpu_vddgp",
+	.soc_id = "cpu_vddsoc",
+	.pu_id = "cpu_vddvpu",
+	.clk1_id = "cpu_clk",
+	.clk2_id = "gpc_dvfs_clk",
+	.gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+	.ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
+	.ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
+	.ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
+	.prediv_mask = 0x1F800,
+	.prediv_offset = 11,
+	.prediv_val = 3,
+	.div3ck_mask = 0xE0000000,
+	.div3ck_offset = 29,
+	.div3ck_val = 2,
+	.emac_val = 0x08,
+	.upthr_val = 25,
+	.dnthr_val = 9,
+	.pncthr_val = 33,
+	.upcnt_val = 10,
+	.dncnt_val = 10,
+	.delay_time = 80,
+};
+
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+				   char **cmdline, struct meminfo *mi)
+{
+}
+
+static const struct imx_pcie_platform_data pcie_data  __initconst = {
+	.pcie_pwr_en	= -EINVAL,
+	.pcie_rst	= MX6_OC_PCIE_RESET,
+	.pcie_wake_up	= -EINVAL,
+	.pcie_dis	= -EINVAL,
+};
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mx6_oc_board_init(void)
+{
+	int i, j;
+	struct clk *clko2;
+	struct clk *new_parent;
+	int rate;
+	int ret = gpio_request_array(mx6_oc_init_gpios,
+			ARRAY_SIZE(mx6_oc_init_gpios));
+
+	if (ret) {
+		printk(KERN_ERR "%s gpio_request_array failed("
+				"%d) for mx6_oc_init_gpios\n", __func__, ret);
+	}
+	IOMUX_SETUP(common_pads);
+
+
+	gp_reg_id = oc_dvfscore_data.reg_id;
+	soc_reg_id = oc_dvfscore_data.soc_id;
+	pu_reg_id = oc_dvfscore_data.pu_id;
+
+	imx6q_add_imx_uart(0, NULL);
+	imx6q_add_imx_uart(1, NULL);
+	imx6q_add_imx_uart(2, &mx6_arm2_uart2_data);
+
+	if (!cpu_is_mx6q()) {
+		ldb_data.ipu_id = 0;
+		ldb_data.sec_ipu_id = 0;
+	}
+	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
+
+	imx6q_add_ipuv3(0, &ipu_data[0]);
+	if (cpu_is_mx6q()) {
+		imx6q_add_ipuv3(1, &ipu_data[1]);
+		j = ARRAY_SIZE(oc_fb_data);
+	} else {
+		j = (ARRAY_SIZE(oc_fb_data) + 1) / 2;
+	}
+	for (i = 0; i < j; i++)
+		imx6q_add_ipuv3fb(i, &oc_fb_data[i]);
+
+	imx6q_add_vdoa();
+	imx6q_add_ldb(&ldb_data);
+	imx6q_add_v4l2_output(0);
+	imx6q_add_v4l2_capture(0, &capture_data);
+	imx6q_add_imx_snvs_rtc();
+
+	imx6q_add_imx_i2c(0, &mx6_oc_i2c_data);
+	imx6q_add_imx_i2c(2, &mx6_oc_i2c_data);
+	i2c_register_board_info(0, mxc_i2c0_board_info,
+			ARRAY_SIZE(mxc_i2c0_board_info));
+	i2c_register_board_info(2, mxc_i2c1_board_info,
+			ARRAY_SIZE(mxc_i2c1_board_info));
+
+	mxc_register_device(&i2c0_i2cmux, &i2c0_i2cmux_data);
+	i2c_register_board_info(3, mxc_i2c3_board_info,
+			ARRAY_SIZE(mxc_i2c3_board_info));
+	i2c_register_board_info(4, mxc_i2c4_board_info,
+			ARRAY_SIZE(mxc_i2c4_board_info));
+
+	mxc_register_device(&i2c2_i2cmux, &i2c2_i2cmux_data);
+	i2c_register_board_info(5, mxc_i2c5_board_info,
+			ARRAY_SIZE(mxc_i2c5_board_info));
+
+	/* SPI */
+	imx6q_add_ecspi(0, &mx6_oc_spi_data);
+	spi_device_init();
+
+	imx6q_add_mxc_hdmi(&hdmi_data);
+
+	imx6q_add_anatop_thermal_imx(1, &mx6_oc_anatop_thermal_data);
+	imx6_init_fec(fec_data);
+	imx6q_add_pm_imx(0, &mx6_oc_pm_data);
+	imx6q_add_sdhci_usdhc_imx(2, &mx6_oc_sd3_data);
+	imx6q_add_sdhci_usdhc_imx(3, &mx6_oc_sd4_data);
+	imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata);
+	imx6_oc_init_usb();
+	imx6q_add_vpu();
+	if (cpu_is_mx6q())
+		imx6q_add_ahci(0, &mx6_oc_sata_data);
+	imx6_init_audio();
+	platform_device_register(&oc_vmmc_reg_devices);
+	imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
+	imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
+	imx6q_add_asrc(&imx_asrc_data);
+
+	/* release USB Hub reset */
+	gpio_set_value(MX6_OC_USB_HUB_RESET, 1);
+
+	imx6q_add_mxc_pwm(3);
+
+	imx6q_add_mxc_pwm_backlight(3, &mx6_oc_pwm4_backlight_data);
+
+	imx6q_add_otp();
+	imx6q_add_viim();
+	imx6q_add_imx2_wdt(0, NULL);
+	imx6q_add_dma();
+
+	imx6q_add_dvfs_core(&oc_dvfscore_data);
+
+	imx6q_add_hdmi_soc();
+	imx6q_add_hdmi_soc_dai();
+
+	clko2 = clk_get(NULL, "clko2_clk");
+	if (IS_ERR(clko2)) {
+		pr_err("can't get CLKO2 clock.\n");
+	} else {
+		new_parent = clk_get(NULL, "osc_clk");
+		if (!IS_ERR(new_parent)) {
+			clk_set_parent(clko2, new_parent);
+			clk_put(new_parent);
+		}
+		rate = clk_round_rate(clko2, 24000000);
+		clk_set_rate(clko2, rate);
+		clk_enable(clko2);
+	}
+	imx6q_add_busfreq();
+
+	imx6q_add_sdhci_usdhc_imx(1, &mx6_oc_sd2_data);
+	platform_device_register(&mx6_oc_vwifi_reg_devices);
+
+	gpio_set_value(MX6_OC_WL_EN, 1);		/* momentarily enable */
+	gpio_set_value(MX6_OC_WL_BT_REG_EN, 1);
+	mdelay(2);
+	gpio_set_value(MX6_OC_WL_EN, 0);
+	gpio_set_value(MX6_OC_WL_BT_REG_EN, 0);
+
+	gpio_free(MX6_OC_WL_EN);
+	gpio_free(MX6_OC_WL_BT_REG_EN);
+	mdelay(1);
+
+	imx6q_add_pcie(&pcie_data);
+
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
+//	regulator_has_full_constraints();
+}
+
+extern void __iomem *twd_base;
+static void __init mx6_oc_timer_init(void)
+{
+	struct clk *uart_clk;
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
+	BUG_ON(!twd_base);
+#endif
+	mx6_clocks_init(32768, 24000000, 0, 0);
+
+	uart_clk = clk_get_sys("imx-uart.0", NULL);
+	early_console_setup(UART2_BASE_ADDR, uart_clk);
+}
+
+static struct sys_timer mx6_oc_timer = {
+	.init   = mx6_oc_timer_init,
+};
+
+static void __init mx6_oc_reserve(void)
+{
+#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
+	phys_addr_t phys;
+
+	if (imx6_gpu_pdata.reserved_mem_size) {
+		phys = memblock_alloc_base(imx6_gpu_pdata.reserved_mem_size,
+					   SZ_4K, SZ_1G);
+		memblock_remove(phys, imx6_gpu_pdata.reserved_mem_size);
+		imx6_gpu_pdata.reserved_mem_base = phys;
+	}
+#endif
+}
+
+/*
+ * initialize __mach_desc_MX6Q_OC data structure.
+ */
+MACHINE_START(MX6_OC, "Freescale i.MX 6 OC Board")
+	.boot_params = MX6_PHYS_OFFSET + 0x100,
+	.fixup = fixup_mxc_board,
+	.map_io = mx6_map_io,
+	.init_irq = mx6_init_irq,
+	.init_machine = mx6_oc_board_init,
+	.timer = &mx6_oc_timer,
+	.reserve = mx6_oc_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-mx6/pads-mx6_oc.h b/arch/arm/mach-mx6/pads-mx6_oc.h
new file mode 100644
index 000000000000..775a3ec075bd
--- /dev/null
+++ b/arch/arm/mach-mx6/pads-mx6_oc.h
@@ -0,0 +1,264 @@
+#undef MX6PAD
+#undef MX6NAME
+#undef MX6
+
+#ifdef FOR_DL_SOLO
+#define MX6(a) MX6DL_##a
+#define MX6PAD(a) MX6DL_PAD_##a
+#define MX6NAME(a) mx6dl_solo_##a
+#else
+#define MX6(a) MX6Q_##a
+#define MX6PAD(a) MX6Q_PAD_##a
+#define MX6NAME(a) mx6q_##a
+#endif
+
+#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
+		PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_50MHZ	MX6Q_USDHC_PAD_CTRL
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ
+#define MX6DL_USDHC_PAD_CTRL_50MHZ	MX6DL_USDHC_PAD_CTRL
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK	MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD	MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define NP(id, pin, pad_ctl) \
+	NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))
+
+#define SD_PINS(id, pad_ctl) \
+	NP(id, CLK, pad_ctl),	\
+	NP(id, CMD, pad_ctl),	\
+	NP(id, DAT0, pad_ctl),	\
+	NP(id, DAT1, pad_ctl),	\
+	NP(id, DAT2, pad_ctl),	\
+	NP(id, DAT3, pad_ctl)
+
+/* Pull/keeper disabled, or with PAD_CTL_PKE to enable */
+#define WEAK (PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_240ohm | PAD_CTL_SPEED_LOW)
+#define WEAK_IRQ (WEAK | PAD_CTL_PKE | PAD_CTL_HYS)
+
+#define WEAK_PD (PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_240ohm | PAD_CTL_SPEED_LOW)
+
+static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
+	/* Audio - SGTL5000 I2C1 */
+	MX6PAD(CSI0_DAT4__AUDMUX_AUD3_TXC),
+	MX6PAD(CSI0_DAT5__AUDMUX_AUD3_TXD),
+	MX6PAD(CSI0_DAT6__AUDMUX_AUD3_TXFS),
+	MX6PAD(CSI0_DAT7__AUDMUX_AUD3_RXD),
+	MX6PAD(GPIO_0__CCM_CLKO),		/* SGTL5000 sys_mclk */
+	NEW_PAD_CTRL(MX6PAD(EIM_A25__GPIO_5_2), WEAK), /* BMUTE active low */
+
+	/* Camera - IPU1 (i2c1)*/
+	MX6PAD(CSI0_DAT8__IPU1_CSI0_D_8),
+	MX6PAD(CSI0_DAT9__IPU1_CSI0_D_9),
+	MX6PAD(CSI0_DAT10__IPU1_CSI0_D_10),
+	MX6PAD(CSI0_DAT11__IPU1_CSI0_D_11),
+	MX6PAD(CSI0_DAT12__IPU1_CSI0_D_12),
+	MX6PAD(CSI0_DAT13__IPU1_CSI0_D_13),
+	MX6PAD(CSI0_DAT14__IPU1_CSI0_D_14),
+	MX6PAD(CSI0_DAT15__IPU1_CSI0_D_15),
+	MX6PAD(CSI0_DAT16__IPU1_CSI0_D_16),
+	MX6PAD(CSI0_DAT17__IPU1_CSI0_D_17),
+	MX6PAD(CSI0_DAT18__IPU1_CSI0_D_18),
+	MX6PAD(CSI0_DAT19__IPU1_CSI0_D_19),
+	MX6PAD(CSI0_DATA_EN__IPU1_CSI0_DATA_EN),
+	MX6PAD(CSI0_MCLK__IPU1_CSI0_HSYNC),
+	MX6PAD(CSI0_VSYNC__IPU1_CSI0_VSYNC),
+	MX6PAD(CSI0_PIXCLK__IPU1_CSI0_PIXCLK),
+	MX6PAD(GPIO_3__CCM_CLKO2),		/* Camera xCLK */
+	NEW_PAD_CTRL(MX6PAD(EIM_D20__GPIO_3_20), WEAK),	/* i2c enable (i2c1) - active high */
+	NEW_PAD_CTRL(MX6PAD(SD1_DAT0__GPIO_1_16), WEAK), /* pin 1 */
+	NEW_PAD_CTRL(MX6PAD(GPIO_6__GPIO_1_6), WEAK),	/* pin 2 */
+	NEW_PAD_CTRL(MX6PAD(GPIO_8__GPIO_1_8), WEAK),	/* Camera Reset, pin 8 */
+
+	/* Display - HDMI EDID(I2C3) */
+	NEW_PAD_CTRL(MX6PAD(EIM_A21__GPIO_2_17), WEAK),	/* i2c enable (I2C3) */
+
+	/*
+	 * Display - LVDS - Backlight
+	 * 6.5 inch is VGA 640x480,
+	 * 10.4 is 1024x768
+	 */
+	NEW_PAD_CTRL(MX6PAD(SD1_CMD__PWM4_PWMO), WEAK),		/* GPIO1[18], J9 pin 10 */
+	NEW_PAD_CTRL(MX6PAD(SD1_DAT1__GPIO_1_17), WEAK),	/* J9 pin 9, also pwm3 */
+
+	/* Ethernet - ENET */
+	MX6PAD(ENET_MDIO__ENET_MDIO),
+	MX6PAD(ENET_MDC__ENET_MDC),
+	MX6PAD(RGMII_TXC__ENET_RGMII_TXC),
+	MX6PAD(RGMII_TD0__ENET_RGMII_TD0),
+	MX6PAD(RGMII_TD1__ENET_RGMII_TD1),
+	MX6PAD(RGMII_TD2__ENET_RGMII_TD2),
+	MX6PAD(RGMII_TD3__ENET_RGMII_TD3),
+	MX6PAD(RGMII_TX_CTL__ENET_RGMII_TX_CTL),
+	MX6PAD(ENET_REF_CLK__ENET_TX_CLK),
+	MX6PAD(RGMII_RXC__ENET_RGMII_RXC),
+	MX6PAD(RGMII_RD0__ENET_RGMII_RD0),
+	MX6PAD(RGMII_RD1__ENET_RGMII_RD1),
+	MX6PAD(RGMII_RD2__ENET_RGMII_RD2),
+	MX6PAD(RGMII_RD3__ENET_RGMII_RD3),
+	MX6PAD(RGMII_RX_CTL__ENET_RGMII_RX_CTL),
+	NEW_PAD_CTRL(MX6PAD(ENET_RXD0__GPIO_1_27), WEAK),		/* Micrel Phy - Reset */
+	NEW_PAD_CTRL(MX6PAD(ENET_TX_EN__GPIO_1_28), WEAK_IRQ),		/* Micrel Phy - Interrupt */
+
+	/*
+	 * I2C1, used by
+	 * SGTL5000
+	 * Camera - thru buffer
+	 * RTC - thru buffer
+	 */
+	MX6PAD(EIM_D21__I2C1_SCL),	/* GPIO3[21] */
+	MX6PAD(EIM_D28__I2C1_SDA),	/* GPIO3[28] */
+
+	/*
+	 * I2C3, used by -
+	 * TSC2004
+	 * J7 i2c connector
+	 *    pin 4 - interrupt - GPIO_9 (same as for tsc2004)
+	 *    pin 5 - sda
+	 *    pin 6 - scl
+	 *
+	 * PCIE connector
+	 * EDID - thru buffer
+	 */
+	MX6PAD(GPIO_5__I2C3_SCL),	/* GPIO1[5] */
+	MX6PAD(GPIO_16__I2C3_SDA),	/* GPIO7[11] */
+
+	/* Keypad */
+	MX6PAD(KEY_COL0__KPP_COL_0),
+	MX6PAD(KEY_COL1__KPP_COL_1),
+	MX6PAD(KEY_COL2__KPP_COL_2),
+	MX6PAD(KEY_ROW0__KPP_ROW_0),
+	MX6PAD(KEY_ROW1__KPP_ROW_1),
+	MX6PAD(KEY_ROW2__KPP_ROW_2),
+	MX6PAD(KEY_ROW3__KPP_ROW_3),
+	MX6PAD(KEY_ROW4__KPP_ROW_4),
+	MX6PAD(GPIO_2__KPP_ROW_6),
+
+	/* PCIE */
+	NEW_PAD_CTRL(MX6PAD(EIM_D22__GPIO_3_22), WEAK),		/* Reset - active low */
+
+	/* Real Time Clock-  RTC(I2C1) */
+	NEW_PAD_CTRL(MX6PAD(EIM_CS0__GPIO_2_23), WEAK), 	/* RTC_I2C_EN - high active (I2C1) */
+	NEW_PAD_CTRL(MX6PAD(EIM_CS1__GPIO_2_24), WEAK_IRQ),	/* RTC_IRQ - low active */
+
+	/* Storage - emmc */
+	SD_PINS(4, USDHC_PAD_CTRL_50MHZ),
+	NEW_PAD_CTRL(MX6PAD(NANDF_D5__GPIO_2_5), WEAK),		/* EMMC Reset */
+
+	/* Storage - SD Card J18 */
+	SD_PINS(3, USDHC_PAD_CTRL_50MHZ),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT5__GPIO_7_0), WEAK_IRQ),	/* SD3_CD */
+
+	/* Storage - SPI NOR */
+	MX6PAD(EIM_D16__ECSPI1_SCLK),
+	MX6PAD(EIM_D17__ECSPI1_MISO),
+	MX6PAD(EIM_D18__ECSPI1_MOSI),
+	NEW_PAD_CTRL(MX6PAD(EIM_D19__GPIO_3_19), WEAK),		/*SS1*/
+
+	/* Touchscreen - tsc2004 - I2C3 */
+	NEW_PAD_CTRL(MX6PAD(GPIO_4__GPIO_1_4), WEAK),		/* Reset - active low */
+	NEW_PAD_CTRL(MX6PAD(GPIO_9__GPIO_1_9), WEAK_IRQ),	/* interrrupt */
+
+	/* UART1  */
+	MX6PAD(SD3_DAT6__UART1_RXD),
+	MX6PAD(SD3_DAT7__UART1_TXD),
+
+	/* UART2/console */
+	MX6PAD(EIM_D27__UART2_RXD),
+	MX6PAD(EIM_D26__UART2_TXD),
+
+	/* USB hub reset */
+	NEW_PAD_CTRL(MX6PAD(GPIO_17__GPIO_7_12), WEAK),		/* USB Hub Reset */
+
+	/* Wireless - bluetooth - Broadcom */
+	MX6PAD(EIM_D23__UART3_CTS),
+	MX6PAD(EIM_D31__UART3_RTS),
+	MX6PAD(EIM_D25__UART3_RXD),
+	MX6PAD(EIM_D24__UART3_TXD),
+        MX6PAD(SD1_CLK__OSC32K_32K_OUT),	/* slow clock */
+	NEW_PAD_CTRL(MX6PAD(NANDF_ALE__GPIO_6_8), WEAK),	/* BT_RESET */
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS2__GPIO_6_15), WEAK),	/* BT_REG_EN */
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), WEAK_IRQ),	/* BT_WAKE_IRQ */
+
+	/* Wireless - WiFi - Broadcom */
+	SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
+	NEW_PAD_CTRL(MX6PAD(NANDF_CLE__GPIO_6_7), WEAK),	/* WL_EN */
+	NEW_PAD_CTRL(MX6PAD(NANDF_WP_B__GPIO_6_9), WEAK_PD),	/* CLK_REQ_IRQ */
+	NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), WEAK_IRQ),	/* WL_WAKE_IRQ */
+	NEW_PAD_CTRL(MX6PAD(NANDF_D0__GPIO_2_0), WEAK),	/* Reserved */
+	NEW_PAD_CTRL(MX6PAD(NANDF_D1__GPIO_2_1), WEAK),	/* Reserved */
+	NEW_PAD_CTRL(MX6PAD(NANDF_D2__GPIO_2_2), WEAK),	/* Reserved */
+	NEW_PAD_CTRL(MX6PAD(NANDF_D3__GPIO_2_3), WEAK),	/* Reserved */
+	NEW_PAD_CTRL(MX6PAD(NANDF_D4__GPIO_2_4), WEAK),	/* Reserved */
+
+	/* 12v supply enable  */
+	NEW_PAD_CTRL(MX6PAD(GPIO_19__GPIO_4_5), WEAK),	/* high active */
+
+	/* Reserved - jumper pins */
+	NEW_PAD_CTRL(MX6PAD(EIM_D30__GPIO_3_30), WEAK),
+//	NEW_PAD_CTRL(MX6PAD(GPIO_1__GPIO_1_1), WEAK),	/* can be USBOTG_ID */
+	MX6PAD(GPIO_1__USBOTG_ID),
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT4__GPIO_7_1), WEAK),
+
+	/* eMMC pads that aren't configured by U-Boot*/
+	MX6PAD(SD4_DAT4__USDHC4_DAT4_200MHZ),
+	MX6PAD(SD4_DAT5__USDHC4_DAT5_200MHZ),
+	MX6PAD(SD4_DAT6__USDHC4_DAT6_200MHZ),
+	MX6PAD(SD4_DAT7__USDHC4_DAT7_200MHZ),
+	0
+};
+
+
+#define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl)	\
+		MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 }
+
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 50, USDHC_PAD_CTRL_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 200, USDHC_PAD_CTRL_200MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 50, USDHC_PAD_CTRL_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 200, USDHC_PAD_CTRL_200MHZ);
+
+#define _50MHZ 0
+#define _100MHZ 1
+#define _200MHZ 2
+#define SD_SPEED_CNT 3
+static iomux_v3_cfg_t * MX6NAME(sd_pads)[] =
+{
+	MX6NAME(sd2_50mhz),
+	MX6NAME(sd2_100mhz),
+	MX6NAME(sd2_200mhz),
+	MX6NAME(sd3_50mhz),
+	MX6NAME(sd3_100mhz),
+	MX6NAME(sd3_200mhz),
+	MX6NAME(sd4_50mhz),
+	MX6NAME(sd4_100mhz),
+	MX6NAME(sd4_200mhz),
+};
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 1076bfc1a61f..5ea35f55ac59 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -131,6 +131,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 #if defined(CONFIG_MACH_MX6_NITROGEN6X)
 	case MACH_TYPE_MX6_NITROGEN6X:
 #endif
+	case MACH_TYPE_MX6_OC:
 		uart_base = MX6Q_UART2_BASE_ADDR;
 		break;
 	case MACH_TYPE_MX6Q_SABRESD:
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 71e4213e8210..c410664eda2d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1116,6 +1116,7 @@ atdgp318		MACH_ATDGP318		ATDGP318		3494
 mx6q_sabreauto		MACH_MX6Q_SABREAUTO	MX6Q_SABREAUTO		3529
 mx6q_sabrelite		MACH_MX6Q_SABRELITE	MX6Q_SABRELITE		3769
 mx6_nitrogen6x		MACH_MX6_NITROGEN6X	MX6_NITROGEN6X		3769
+mx6_oc			MACH_MX6_OC		MX6_OC			3770
 mx6q_sabresd		MACH_MX6Q_SABRESD	MX6Q_SABRESD		3980
 mx6q_arm2		MACH_MX6Q_ARM2		MX6Q_ARM2		3837
 mx6sl_arm2		MACH_MX6SL_ARM2		MX6SL_ARM2		4091