diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-08-22 23:53:25 +0800 |
|---|---|---|
| committer | Sasha Levin <alexander.levin@verizon.com> | 2016-10-02 13:39:14 -0400 |
| commit | 82ae68a84f2ce4de5bbcff7976bbfa46096862b5 (patch) | |
| tree | b0d0e83cd1ef3078810e0eecce9a2179976cd32e /arch | |
| parent | 6558ce65ea89058a9b472ab994154931988efcae (diff) | |
ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx
[ Upstream commit 8aade778f787305fdbfd3c1d54e6b583601b5902 ]
i.MX6SX has bypass PMIC ready function, as this function
is normally NOT enabled on the board design, so we need
to bypass the PMIC ready pin check during DSM mode resume
flow, otherwise, the internal DSM resume logic will be
waiting for this signal to be ready forever and cause
resume fail.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Fixes: ff843d621bfc ("ARM: imx: add suspend support for i.mx6sx")
Cc: <stable@vger.kernel.org>
Tested-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 6a7c6fc780cc..4627c862beac 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -288,7 +288,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) + if (cpu_is_imx6sl() || cpu_is_imx6sx()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; |