diff options
| author | Min-wuk Lee <mlee@nvidia.com> | 2011-03-15 14:26:56 +0900 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-03-16 09:47:22 -0800 |
| commit | 8d8e4e29c22414acc5cd4dce405a3ad3a55cf307 (patch) | |
| tree | 92c3774b58db61d0e5b02e6b7c100a3451d82573 /arch | |
| parent | fe13d9d4f67c9d4e68b6c31d904efe51a22bdc52 (diff) | |
spi: tegra: slink reset for error
Whenever the error or timeout happen,
slink controller needs to be reset.
This is applied when tegra spi is
used as slave.
This change will disable rx/tx path, then,
clear BSY bit by slink controller reset
in case time out happens.
Bug 775644
Change-Id: I966ab1979b4934aebf163c59db7839c0d838cfd3
Reviewed-on: http://git-master/r/22928
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Tested-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rwxr-xr-x[-rw-r--r--] | arch/arm/mach-tegra/spi_tegra_slave.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/spi_tegra_slave.c b/arch/arm/mach-tegra/spi_tegra_slave.c index 48492ab9253a..21fca5bf0a61 100644..100755 --- a/arch/arm/mach-tegra/spi_tegra_slave.c +++ b/arch/arm/mach-tegra/spi_tegra_slave.c @@ -36,6 +36,7 @@ #include <mach/dma.h> #include <mach/spi.h> +#include <mach/clk.h> #define SLINK_COMMAND 0x000 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) @@ -463,6 +464,21 @@ static void complete_operation(struct tegra_dma_req *req) /*In order to make sure Rx fifo fluch is completed.*/ while (spi_tegra_readl(tspi, SLINK_STATUS)&SLINK_RX_FLUSH) ; + /* + * rx disable and tx disable + */ + val_write = spi_tegra_readl(tspi, SLINK_COMMAND2); + val_write &= ~SLINK_RXEN; + val_write &= ~SLINK_TXEN; + spi_tegra_writel(tspi, val_write, SLINK_COMMAND2); + + /* + * reset the slink controller + * */ + tegra_periph_reset_assert(tspi->clk); + udelay(50); + tegra_periph_reset_deassert(tspi->clk); + udelay(50); } /* the SPI controller may come back with both the BSY and RDY bits |