diff options
| author | Danny Nold <dannynold@freescale.com> | 2011-05-02 12:35:05 -0500 |
|---|---|---|
| committer | Danny Nold <dannynold@freescale.com> | 2011-05-04 13:38:18 -0500 |
| commit | 10dd303550c35eaea8745ae46688b9b87b37f257 (patch) | |
| tree | 7deec8d26d68396988b5903500468e2ed5d00c18 /arch | |
| parent | afdb1393f80f9155490963af89bd31194d024686 (diff) | |
ENGR00142954 - MSL clocks: correct APLL settings to prevent random PxP lockups
- Add appropriate bit settings to ANADIG_MISC to improve APLL signal integrity
and prevent intermittent PxP lockups
Signed-off-by: Danny Nold <dannynold@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 4 |
2 files changed, 16 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 35f88a294c11..f93aa3a924ca 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -308,18 +308,28 @@ static struct clk ckil_clk = { static int apll_enable(struct clk *clk) { - __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); + /* Set bit to flush multiple edges out of PLL vco */ + __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF, + apll_base + MXC_ANADIG_MISC_SET); + + __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_SET); if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) & MXC_ANADIG_APLL_LOCK, 80000)) panic("apll_enable failed!\n"); + /* Clear after relocking, then wait 10 us */ + __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF, + apll_base + MXC_ANADIG_MISC_CLR); + + udelay(10); + return 0; } static void apll_disable(struct clk *clk) { - __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR); + __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_CLR); } static unsigned long apll_get_rate(struct clk *clk) diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index ee862024c9ec..8979d217b949 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -111,6 +111,10 @@ #define MXC_ANADIG_PFD4_STABLE (1 << 6) #define MXC_ANADIG_PFD4_FRAC_OFFSET 0 +#define MXC_ANADIG_REF_SELFBIAS_OFF (1 << 20) +#define MXC_ANADIG_PLL_HOLD_RING_OFF (1 << 7) +#define MXC_ANADIG_PLL_POWERUP (1 << 0) + #define MXC_ANADIG_APLL_LOCK (1 << 31) #define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) #define MXC_ANADIG_PFD_DIS_OFFSET 16 |