ENGR00138731-2: MX5X: Update DVFS-CORE to support more than 2 operating points.

DVFS-CORE has been updated to support different working points.
Move the dvfs_core working point structure into platform specific files.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

6 files changed, 133 insertions, 33 deletions

diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c
index d598a0663e68..349a9319e476 100644
--- a/arch/arm/mach-mx5/bus_freq.c
+++ b/arch/arm/mach-mx5/bus_freq.c
@@ -136,12 +136,6 @@ extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void __iomem *ccm_base;
 extern void __iomem *databahn_base;
 
-struct dvfs_wp dvfs_core_setpoint[] = {
-						{33, 8, 33, 10, 10, 0x08},
-						{26, 0, 33, 20, 10, 0x08},
-						{28, 8, 33, 20, 30, 0x08},
-						{29, 0, 33, 20, 10, 0x08},};
-
 static DEFINE_SPINLOCK(voltage_lock);
 struct mutex bus_freq_mutex;
 
@@ -201,6 +195,7 @@ void enter_lpapm_mode_mx50()
 
 	set_ddr_freq(LP_APM_CLK);
 	/* Set the parent of main_bus_clk to be PLL3 */
+
 	clk_set_parent(main_bus_clk, pll3);
 
 	/* Set the AHB dividers to be 2.
@@ -258,12 +253,11 @@ void enter_lpapm_mode_mx50()
 		/* Set the divider to ARM_PODF to 3. */
 		__raw_writel(0x02, MXC_CCM_CACRR);
 
-		clk_set_rate(pll1, 160000000);
+		clk_set_rate(pll1, cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate);
 		clk_set_parent(pll1_sw_clk, pll1);
 		/* Set the divider to ARM_PODF to 1. */
 		__raw_writel(0x0, MXC_CCM_CACRR);
 	}
-
 	udelay(100);
 }
 
@@ -506,7 +500,7 @@ void exit_lpapm_mode_mx50(int high_bus_freq)
 		/* Set the divider to ARM_PODF to 3, cpu is at 160MHz. */
 		__raw_writel(0x02, MXC_CCM_CACRR);
 
-		clk_set_rate(pll1, 800000000);
+		clk_set_rate(pll1, cpu_wp_tbl[0].pll_rate);
 		clk_set_parent(pll1_sw_clk, pll1);
 		/* Set the divider to ARM_PODF to 5. */
 		__raw_writel(0x4, MXC_CCM_CACRR);
@@ -602,7 +596,6 @@ void exit_lpapm_mode_mx50(int high_bus_freq)
 		med_bus_freq_mode = 0;
 		set_ddr_freq(ddr_normal_rate);
 	}
-
 	spin_unlock_irqrestore(&ddr_freq_lock, flags);
 
 	udelay(100);
diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 9ca55fb59709..369c14ff6e20 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -108,6 +108,7 @@
 extern int __init mx50_arm2_init_mc13892(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
+extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp);
 static int max17135_regulator_init(struct max17135 *max17135);
 static int num_cpu_wp = 2;
 
@@ -306,7 +307,14 @@ static struct mxc_bus_freq_platform_data bus_freq_data = {
 	.lp_reg_id = "SW2",
 };
 
-/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
+struct dvfs_wp dvfs_core_setpoint[] = {
+	{33, 13, 33, 10, 10, 0x08}, /* 800MHz*/
+	{28, 8, 33, 10, 10, 0x08},   /* 400MHz */
+	{20, 0, 33, 20, 10, 0x08},   /* 160MHz*/
+	{28, 8, 33, 20, 30, 0x08},   /*160MHz, AHB 133MHz, LPAPM mode*/
+	{29, 0, 33, 20, 10, 0x08},}; /* 160MHz, AHB 24MHz */
+
+/* working point(wp): 0 - 800MHz; 1 - 400MHz, 2 - 160MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
 	 .pll_rate = 800000000,
@@ -319,15 +327,22 @@ static struct cpu_wp cpu_wp_auto[] = {
 	 .cpu_voltage = 1050000,},
 	{
 	 .pll_rate = 800000000,
+	 .cpu_rate = 400000000,
+	 .cpu_podf = 1,
+	 .cpu_voltage = 1050000,},
+	{
+	 .pll_rate = 800000000,
 	 .cpu_rate = 160000000,
-	 .pdf = 4,
-	 .mfi = 8,
-	 .mfd = 2,
-	 .mfn = 1,
 	 .cpu_podf = 4,
 	 .cpu_voltage = 850000,},
 };
 
+static struct dvfs_wp *mx50_arm2_get_dvfs_core_table(int *wp)
+{
+	*wp = ARRAY_SIZE(dvfs_core_setpoint);
+	return dvfs_core_setpoint;
+}
+
 static struct cpu_wp *mx50_arm2_get_cpu_wp(int *wp)
 {
 	*wp = num_cpu_wp;
@@ -1095,6 +1110,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 
 	get_cpu_wp = mx50_arm2_get_cpu_wp;
 	set_num_cpu_wp = mx50_arm2_set_num_cpu_wp;
+	get_dvfs_core_wp = mx50_arm2_get_dvfs_core_table;
 }
 
 static void __init mx50_arm2_io_init(void)
diff --git a/arch/arm/mach-mx5/mx50_rdp.c b/arch/arm/mach-mx5/mx50_rdp.c
index 0f71fa3d9293..eb30b1b65731 100644
--- a/arch/arm/mach-mx5/mx50_rdp.c
+++ b/arch/arm/mach-mx5/mx50_rdp.c
@@ -120,8 +120,15 @@
 extern int __init mx50_rdp_init_mc13892(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
+extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp);
+
+static void mx50_suspend_enter(void);
+static void mx50_suspend_exit(void);
+static void fec_gpio_iomux_init(void);
+static void fec_gpio_iomux_deinit(void);
+
 static int max17135_regulator_init(struct max17135 *max17135);
-static int num_cpu_wp = 2;
+static int num_cpu_wp = 3;
 
 static iomux_v3_cfg_t mx50_rdp[] = {
 	/* SD1 */
@@ -450,7 +457,7 @@ static struct mxc_dvfs_platform_data dvfs_core_data = {
 	.upcnt_val = 10,
 	.dncnt_val = 10,
 	.delay_time = 80,
-	.num_wp = 2,
+	.num_wp = 3,
 };
 
 static struct mxc_bus_freq_platform_data bus_freq_data = {
@@ -458,7 +465,14 @@ static struct mxc_bus_freq_platform_data bus_freq_data = {
 	.lp_reg_id = "SW2",
 };
 
-/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
+static struct dvfs_wp dvfs_core_setpoint[] = {
+	{33, 13, 33, 10, 10, 0x08}, /* 800MHz*/
+	{28, 8, 33, 10, 10, 0x08},   /* 400MHz */
+	{20, 0, 33, 20, 10, 0x08},   /* 160MHz*/
+	{28, 8, 33, 20, 30, 0x08},   /*160MHz, AHB 133MHz, LPAPM mode*/
+	{29, 0, 33, 20, 10, 0x08},}; /* 160MHz, AHB 24MHz */
+
+/* working point(wp): 0 - 800MHz; 1 - 400MHz, 2 - 160MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
 	 .pll_rate = 800000000,
@@ -471,15 +485,22 @@ static struct cpu_wp cpu_wp_auto[] = {
 	 .cpu_voltage = 1050000,},
 	{
 	 .pll_rate = 800000000,
+	 .cpu_rate = 400000000,
+	 .cpu_podf = 1,
+	 .cpu_voltage = 1050000,},
+	{
+	 .pll_rate = 800000000,
 	 .cpu_rate = 160000000,
-	 .pdf = 4,
-	 .mfi = 8,
-	 .mfd = 2,
-	 .mfn = 1,
 	 .cpu_podf = 4,
 	 .cpu_voltage = 850000,},
 };
 
+static struct dvfs_wp *mx50_rdp_get_dvfs_core_table(int *wp)
+{
+	*wp = ARRAY_SIZE(dvfs_core_setpoint);
+	return dvfs_core_setpoint;
+}
+
 static struct cpu_wp *mx50_rdp_get_cpu_wp(int *wp)
 {
 	*wp = num_cpu_wp;
@@ -1410,6 +1431,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 
 	get_cpu_wp = mx50_rdp_get_cpu_wp;
 	set_num_cpu_wp = mx50_rdp_set_num_cpu_wp;
+	get_dvfs_core_wp = mx50_rdp_get_dvfs_core_table;
 }
 
 static void __init mx50_rdp_io_init(void)
@@ -1518,7 +1540,6 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&busfreq_device, &bus_freq_data);
 	mxc_register_device(&pm_device, &mx50_pm_data);
 	mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
-
 	if (enable_keypad)
 		mxc_register_device(&mxc_keypad_device, &keypad_plat_data);
 
diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c
index 3188cc77bf45..0cfe5a286343 100644
--- a/arch/arm/mach-mx5/mx51_3stack.c
+++ b/arch/arm/mach-mx5/mx51_3stack.c
@@ -103,9 +103,17 @@ extern int __init mx51_3stack_init_mc13892(void);
 extern void __init mx51_3stack_io_init(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
+extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp);
+
 static int num_cpu_wp = 3;
 static bool debug_board_present;
 
+static struct dvfs_wp dvfs_core_setpoint[] = {
+						{33, 8, 33, 10, 10, 0x08},
+						{26, 0, 33, 20, 10, 0x08},
+						{28, 8, 33, 20, 30, 0x08},
+						{29, 0, 33, 20, 10, 0x08},};
+
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -129,14 +137,16 @@ static struct cpu_wp cpu_wp_auto[] = {
 	{
 	 .pll_rate = 800000000,
 	 .cpu_rate = 166250000,
-	 .pdf = 4,
-	 .mfi = 8,
-	 .mfd = 2,
-	 .mfn = 1,
 	 .cpu_podf = 4,
 	 .cpu_voltage = 850000,},
 };
 
+static struct dvfs_wp *mx51_3stack_get_dvfs_core_table(int *wp)
+{
+	*wp = ARRAY_SIZE(dvfs_core_setpoint);
+	return dvfs_core_setpoint;
+}
+
 struct cpu_wp *mx51_3stack_get_cpu_wp(int *wp)
 {
 	*wp = num_cpu_wp;
@@ -917,6 +927,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 
 	get_cpu_wp = mx51_3stack_get_cpu_wp;
 	set_num_cpu_wp = mx51_3stack_set_num_cpu_wp;
+	get_dvfs_core_wp = mx51_3stack_get_dvfs_core_table;
 }
 
 static struct mxc_gps_platform_data gps_data = {
diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c
index 7340c9d780f7..318bf367a18e 100644
--- a/arch/arm/mach-mx5/mx51_babbage.c
+++ b/arch/arm/mach-mx5/mx51_babbage.c
@@ -98,6 +98,8 @@
 extern int __init mx51_babbage_init_mc13892(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
+extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp);
+
 static int num_cpu_wp = 3;
 
 static iomux_v3_cfg_t mx51babbage_pads[] = {
@@ -237,6 +239,12 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
 	MX51_PAD_OWIRE_LINE__SPDIF_OUT,
 };
 
+static struct dvfs_wp dvfs_core_setpoint[] = {
+						{33, 8, 33, 10, 10, 0x08},
+						{26, 0, 33, 20, 10, 0x08},
+						{28, 8, 33, 20, 30, 0x08},
+						{29, 0, 33, 20, 10, 0x08},};
+
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -260,10 +268,6 @@ static struct cpu_wp cpu_wp_auto[] = {
 	{
 	 .pll_rate = 800000000,
 	 .cpu_rate = 166250000,
-	 .pdf = 4,
-	 .mfi = 8,
-	 .mfd = 2,
-	 .mfn = 1,
 	 .cpu_podf = 4,
 	 .cpu_voltage = 850000,},
 };
@@ -312,6 +316,12 @@ static struct fb_videomode video_modes[] = {
 	 FB_VMODE_NONINTERLACED,
 	 0,},
 };
+static struct dvfs_wp *mx51_babbage_get_dvfs_core_table(int *wp)
+{
+	*wp = ARRAY_SIZE(dvfs_core_setpoint);
+	return dvfs_core_setpoint;
+}
+
 
 struct cpu_wp *mx51_babbage_get_cpu_wp(int *wp)
 {
@@ -995,6 +1005,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 
 	get_cpu_wp = mx51_babbage_get_cpu_wp;
 	set_num_cpu_wp = mx51_babbage_set_num_cpu_wp;
+	get_dvfs_core_wp = mx51_babbage_get_dvfs_core_table;
 
 	for_each_tag(mem_tag, tags) {
 		if (mem_tag->hdr.tag == ATAG_MEM) {
diff --git a/arch/arm/mach-mx5/mx53_wp.c b/arch/arm/mach-mx5/mx53_wp.c
index a09cb735c1d0..f40a979aaf3d 100644
--- a/arch/arm/mach-mx5/mx53_wp.c
+++ b/arch/arm/mach-mx5/mx53_wp.c
@@ -21,6 +21,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
 #include "mx53_wp.h"
 
 /*!
@@ -32,9 +33,36 @@
  */
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
+extern struct dvfs_wp *(*get_dvfs_core_wp)(int *wp);
+
 static int num_cpu_wp;
 static struct cpu_wp *cpu_wp_table;
 
+static struct dvfs_wp *dvfs_core_setpoint;
+static int num_dvfs_core_setpoint;
+
+/* Place holder for dvfs_core setpoints for AEC parts */
+static struct dvfs_wp dvfs_core_setpoint_aec[] = {
+				{33, 0, 33, 10, 10, 0x08} }; /*800MHz*/
+
+/* Place holder for dvfs_core setpoints for 1.2GHz parts */
+static struct dvfs_wp dvfs_core_setpoint_ces_1_2G[] = {
+			{33, 25, 33, 10, 10, 0x08}, /*1_2GHz*/
+			{30, 18, 33, 20, 10, 0x08}, /* 800MHz */
+			{25, 8, 33, 20, 10, 0x08}, /* 400MHz */
+			{23, 0, 33, 20, 10, 0x08}, /* 160MHz */
+			{28, 8, 33, 20, 30, 0x08}, /*160MHz, 133MHz */
+			{29, 0, 33, 20, 10, 0x08},}; /* 160MHz, 50MHz. */
+
+/* Place holder for dvfs_core setpoints for 1 GHz parts */
+static struct dvfs_wp dvfs_core_setpoint_ces[] = {
+			{33, 25, 33, 10, 10, 0x08}, /*1GHz*/
+			{30, 18, 33, 20, 10, 0x08}, /* 800MHz */
+			{25, 8, 33, 20, 10, 0x08}, /* 400MHz */
+			{23, 0, 33, 20, 10, 0x08}, /* 160MHz */
+			{28, 8, 33, 20, 30, 0x08}, /*160MHz, 133MHz */
+			{29, 0, 33, 20, 10, 0x08},}; /* 160MHz, 50MHz. */
+
 /* working point for auto*/
 static struct cpu_wp cpu_wp_aec[] = {
 	{
@@ -71,8 +99,12 @@ static struct cpu_wp cpu_wp_ces[] = {
 	 {
 	  .pll_rate = 800000000,
 	  .cpu_rate = 400000000,
-	  .cpu_podf = 1,
-	  .cpu_voltage = 950000,},
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 1,
+	 .cpu_voltage = 950000,},
 	{
 	 .pll_rate = 800000000,
 	 .cpu_rate = 160000000,
@@ -121,6 +153,12 @@ static struct cpu_wp cpu_wp_ces_1_2g[] = {
 	 .cpu_voltage = 900000,},
 };
 
+static struct dvfs_wp *mx53_get_dvfs_core_table(int *wp)
+{
+	/* Add 2 to num_cpu_wp to handle LPAPM mode transitions. */
+	*wp = num_dvfs_core_setpoint;
+	return dvfs_core_setpoint;
+}
 
 struct cpu_wp *mx53_get_cpu_wp(int *wp)
 {
@@ -138,20 +176,30 @@ void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num)
 {
 	get_cpu_wp = mx53_get_cpu_wp;
 	set_num_cpu_wp = mx53_set_num_cpu_wp;
+	get_dvfs_core_wp = mx53_get_dvfs_core_table;
 
 	switch (part_num) {
 	case IMX53_CEC_1_2G:
 		cpu_wp_table = cpu_wp_ces_1_2g;
 		num_cpu_wp = ARRAY_SIZE(cpu_wp_ces_1_2g);
+		dvfs_core_setpoint = dvfs_core_setpoint_ces_1_2G;
+		num_dvfs_core_setpoint =
+				ARRAY_SIZE(dvfs_core_setpoint_ces_1_2G);
 		break;
 	case IMX53_CEC:
 		cpu_wp_table = cpu_wp_ces;
 		num_cpu_wp = ARRAY_SIZE(cpu_wp_ces);
+		dvfs_core_setpoint = dvfs_core_setpoint_ces;
+		num_dvfs_core_setpoint =
+				ARRAY_SIZE(dvfs_core_setpoint_ces);
 		break;
 	case IMX53_AEC:
 	default:
 		cpu_wp_table = cpu_wp_aec;
 		num_cpu_wp = ARRAY_SIZE(cpu_wp_aec);
+		dvfs_core_setpoint = dvfs_core_setpoint_aec;
+		num_dvfs_core_setpoint =
+				ARRAY_SIZE(dvfs_core_setpoint_aec);
 		break;
 	}
 }