diff options
| author | Anson Huang <b20788@freescale.com> | 2013-08-26 11:40:17 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-03 23:01:44 -0500 |
| commit | edeafa4f9790d9b8736c836691dee381c5fcae5c (patch) | |
| tree | 417035ef6d5848a2ac90ba48fdc2507332e4beef /arch | |
| parent | 601d80666415441899b4513f3f0a7de81d54cfb4 (diff) | |
ENGR00276652 ARM: mx6: Use IOMUXC irq instead of #125
Some boards' irq #125 are not pending, so we need to
force irq #32 to be pending manually to ensure CCM is
in correct stat before entering low power mode. Using
irq #32 is more reliable than #125, as we can trigger
it manually. See below commit for detail of CCM LPM
issue:
commit 04b5224599fef16ef3a1856dd1b3205360b772c1
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/cpu.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 8 |
2 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index a65ad81e666d..50986da88a5d 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -149,6 +149,12 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x50); iounmap(base); + /* Force IOMUXC irq to be pending for CCM LPM */ + base = IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR); + reg = __raw_readl(base + 0x4); + reg |= 0x1000; + __raw_writel(reg, base + 0x4); + /* Allow SCU_CLK to be disabled when all cores are in WFI*/ base = IO_ADDRESS(SCU_BASE_ADDR); reg = __raw_readl(base); diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index ff1feda30f5b..1ec072abcefe 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -113,12 +113,12 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) * is a dsm_wakeup_signal, which means the wakeup source * must be seen by GPC, then CCM will clean its state machine * and re-sample necessary signal to decide whether it can - * enter LPM mode. Here we use the forever pending irq #125, + * enter LPM mode. Here we force irq #32 to be always pending, * unmask it before we enable LPM mode and mask it after LPM * is enabled, this flow will make sure CCM state machine in * reliable state before we enter LPM mode. */ - gpc_mask_single_irq(MXC_INT_CHEETAH_PARITY, false); + gpc_mask_single_irq(MXC_INT_GPR, false); switch (mode) { case WAIT_CLOCKED: @@ -177,7 +177,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) break; default: printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); - gpc_mask_single_irq(MXC_INT_CHEETAH_PARITY, true); + gpc_mask_single_irq(MXC_INT_GPR, true); return; } @@ -275,7 +275,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) } } __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); - gpc_mask_single_irq(MXC_INT_CHEETAH_PARITY, true); + gpc_mask_single_irq(MXC_INT_GPR, true); } extern int tick_broadcast_oneshot_active(void); |