diff options
| author | Phoenix Jung <pjung@nvidia.com> | 2014-05-01 15:31:14 +0900 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2014-05-12 16:34:27 -0700 |
| commit | 854199e6f5fb7d898154cd80c914fdbf542abcf5 (patch) | |
| tree | caec3ae47e823e14185183eb1be615b7aceb4746 /arch | |
| parent | 223d7bdd76b73da29e0bd05ef1455d59ea19216c (diff) | |
arm: tegra: vcm30t124: Update DT for android kernel
Add DT entries for SATA and sdhci
Bug 1500533
Bug 1440706
Change-Id: I6def2df9db16b454a33e9e236d3005dddc19057c
Signed-off-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-on: http://git-master/r/403980
(cherry picked from commit e4c5d49dace7a6e36d8dda3e3f633df9fa374e85)
Reviewed-on: http://git-master/r/405770
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Reviewed-by: Raveesh Kote <rkote@nvidia.com>
Reviewed-by: Vijaya Bhaskar <vbhaskar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/tegra124-ardbeg-vcm30-t124.dts | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124-ardbeg-vcm30-t124.dts b/arch/arm/boot/dts/tegra124-ardbeg-vcm30-t124.dts index d512eb7f4832..40e50fffda8d 100644 --- a/arch/arm/boot/dts/tegra124-ardbeg-vcm30-t124.dts +++ b/arch/arm/boot/dts/tegra124-ardbeg-vcm30-t124.dts @@ -33,6 +33,7 @@ #size-cells = <2>; chosen { + nvidia,tegra-hypervisor-mode; }; i2c@7000c400 { @@ -126,6 +127,48 @@ status = "okay"; }; + sata@0x70020000 { + status = "okay"; + nvidia,enable-sata-port; + }; + + sdhci@700b0600 { + tap-delay = <0x4>; + trim-delay = <0x4>; + ddr-trim-delay = <0x4>; + mmc-ocr-mask = <0>; + uhs_mask = <0x20>; + bus-width = <8>; + built-in; + ddr-clk-limit = <51000000>; + max-clk-limit = <200000000>; + status = "okay"; + }; + + sdhci@700b0200 { + tap-delay = <0x1>; + trim-delay = <0x3>; + ddr-trim-delay = <0x3>; + mmc-ocr-mask = <0>; + uhs_mask = <0x20>; + built-in; + ddr-clk-limit = <30000000>; + max-clk-limit = <51000000>; + status = "okay"; + }; + + sdhci@700b0400 { + cd-gpios = <&gpio 133 0>; + wp-gpios = <&gpio 132 0>; + tap-delay = <0>; + trim-delay = <3>; + mmc-ocr-mask = <3>; + uhs_mask = <0x2F>; + bus-width = <4>; + max-clk-limit = <50000000>; + status = "okay"; + }; + /* All ardbeg devices are using ttyTHS2 port for BT. * So changed the enumerated ordering of uartd from ttyTHS3 to ttyTHS2 */ |